鈥?/div>
Available under terms of the SignOnce IP License
Complies with USB protocol revision 1.1
Supports VCI to the application bus
Supports full-speed (12 Mbps) signaling bit rate
Supports low-speed (1.5 Mbps) signaling bit rate
Handles USB protocol
Handles USB device states
Clock and data recovery from USB
Microprocessor independent
Includes Suspend/Resume logic
Performs cyclic redundancy checks (CRC) with CRC5
checking, and CRC16 generation and checking
Supports up to fifteen configurations, with each
configuration supporting fifteen interfaces and each
interface handling up to fifteen alternate settings
Enables physical endpoint number programming and
supports up to 16 bidirectional logical endpoints
Features (contd)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maintains data toggle bits
Enables user-configured endpoint information
Provides understanding and decoding of standard USB
commands to endpoint zero
Provides the option to decode the Get Descriptor
command or to pass the command to the application for
decoding
Supports class/vendor commands by passing the Setup
transactions to the application
Supports up to 15 string descriptors
鈥?/div>
鈥?/div>
鈥?/div>
Table 1: Core Implementation Data
1
Supported
Family
Virtex鈩?II
Spartan鈩?II
Virtex鈩?E
Device Tested
XC2V1000-5
XC2S200-5
XCV300E-8
CLB
Slices
1036
1029
1029
Clock
IOBs
2
2
2
2
IOBs
2
117
117
117
Performance
(MHz)
3
12
12
12
Xilinx Tools
Alliance 3.3iSP8
Alliance 3.3iSP8
Alliance 3.3iSP8
Special
Features
None
None
None
Notes:
1. These numbers reached with the following options, with the sample design: hard-coded registers, application and UDC using same
clock, the core does not decode get_descriptor, 1 interface, 1 alternate, 1 additional endpoint (bulk out), endpoint 0 maxpktsize is 8
bytes, endpoint 1 maxpktsize is 8 bytes
2. Assuming all core signals are routed off-chip.
3. Minimum guaranteed speed.
May 20, 2002
1
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