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XC2C384 Datasheet

  • XC2C384

  • CoolRunner-II CPLD Family

  • 14頁(yè)

  • XILINX   XILINX

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CoolRunner-II CPLD Family
0
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DS090 (v2.5) June 28, 2005
Product Specification
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
- SSTL2_1,SSTL3_1, and HSTL_1 on 128
macrocell and denser devices
- Hot pluggable
PLA architecture
- Superior pinout retention
- 100% product term routability across function block
Wide package availability including fine pitch:
- Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, PLCC, and QFN packages
- Pb-free available for all packages
Design entry/verification using Xilinx and industry
standard CAE tools
Free software support for all densities using Xilinx
WebPACK鈩?/div>
Industry leading nonvolatile 0.18 micron CMOS
process
- Guaranteed 1,000 program/erase cycles
- Guaranteed 20 year data retention
-
Features
鈥?/div>
Optimized for 1.8V systems
- Industry鈥檚 fastest low power CPLD
- Densities from 32 to 512 macrocells
Industry鈥檚 best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation 鈥?1.5V to 3.3V
Advanced system features
- Fastest in system programming
路
1.8V ISP using IEEE 1532 (JTAG) interface
- On-The-Fly Reconfiguration (OTF)
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt trigger input (per pin)
- Multiple I/O banks on all devices
- Unsurpassed low power management
路
DataGATE external signal control
- Flexible clocking modes
路
Optional DualEDGE triggered registers
路
Clock divider (梅 2,4,6,8,10,12,14,16)
路
CoolCLOCK
- Global signal options with macrocell control
路
Multiple global clocks with phase selection per
macrocell
路
Multiple global output enables
路
Global set/reset
- Abundant product term clocks, output enables and
set/resets
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pullup on select
I/O pins
- Optional configurable grounds on unused I/Os
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Family Overview
Xilinx CoolRunner鈩?II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD fam-
ily with the extremely low power versatility of the XPLA3鈩?/div>
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are com-
bined into a single family that is easy to use and cost effec-
tive. Clocking techniques and other power saving features
extend the users鈥?power budget. The design features are
supported starting with Xilinx ISE 4.1i ISE WebPACK. Addi-
tional details can be found in
Further Reading,
page 13.
Table 1
shows the macrocell capacity and key timing
parameters for the CoolRunner-II CPLD family.
Table 1:
CoolRunner-II CPLD Family Parameters
XC2C32A
Macrocells
Max I/O
T
PD
(ns)
T
SU
(ns)
T
CO
(ns)
F
SYSTEM1
(MHz)
32
33
3.8
1.9
3.7
323
XC2C64A
64
64
4.6
2.0
3.9
263
XC2C128
128
100
5.7
2.4
4.2
244
XC2C256
256
184
5.7
2.4
4.5
256
XC2C384
384
240
7.1
2.9
5.8
217
XC2C512
512
270
7.1
2.6
5.8
179
漏 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS090 (v2.5) June 28, 2005
Product Specification
www.xilinx.com
1

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