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X5083V8-1.8 Datasheet

  • X5083V8-1.8

  • SPI Serial EEPROM with Supervisory Features

  • 140.52KB

  • 20頁

  • ETC

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Replaces X25383
X5083
CPU Supervisor with 8Kbit SPI EEPROM
FEATURES
鈥?Selectable time out watchdog timer
鈥?Low V
CC
detection and reset assertion
鈥擣ive standard reset threshold voltages
鈥擱e-program low V
CC
reset threshold voltage
using special programming sequence.
鈥擱eset signal valid to V
CC
= 1V
鈥?Long battery life with low power consumption
鈥?lt;50碌A(chǔ) max standby current, watchdog on
鈥?lt;1碌A(chǔ) max standby current, watchdog off
鈥?lt;400碌A(chǔ) max active current during read
鈥?1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V power
supply versions
鈥?8Kbits of EEPROM鈥?m write cycle endurance
鈥?Save critical data with Block Lock
鈩?/div>
memory
鈥擝lock lock first or last page, any 1/4 or lower 1/2
of EEPROM array
鈥?Built-in inadvertent write protection
鈥擶rite enable latch
鈥擶rite protect pin
鈥?3.3MHz clock rate
鈥?Minimize programming time
鈥?6 byte page write mode
鈥擲elf-timed write cycle
鈥?ms write cycle time (typical)
鈥?SPI modes (0,0 & 1,1)
鈥?Available packages
鈥?-lead TSSOP, 8-lead SOIC
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Protect Logic
RESET
Status
Register
EEPROM Array
16 Bytes
240 Bytes
256 Bytes
256 Bytes
240 Bytes
16 Bytes
+
DESCRIPTION
This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Super-
vision, and Block Lock Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to
stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The device鈥檚 low V
CC
detection circuitry protects the
user鈥檚 system from low voltage conditions, resetting
the system when V
CC
falls below the minimum V
CC
trip point. RESET is asserted until V
CC
returns to the
proper operating level and stabilizes. Five industry
standard V
TRIP
thresholds are available, however, Xicor鈥檚
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to 鏗乶e-tune the thresh-
old for applications requiring higher precision.
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
V
CC
V
TRIP
REV 1.1 9/25/00
-
Power On and
Low Voltage
Reset
Generation
Characteristics subject to change without notice.
www.xicor.com
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X5083V8-1.8相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...

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