鈥?/div>
DATA
Polling
鈥擳oggle Bit Polling
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 E
2
PROM. It is fabricated with
Xicor鈥檚 proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvolatile
memory.
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24碌s/byte write cycle and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA
Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data
retention of 100 years.
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
SOIC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28HC256
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
X28HC256
A7
LCC
PLCC
VCC
A12
A14
A13
WE
NC
TSOP
4
3
2
1 32 31 30
29
28
27
26
25
24
23
22
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A3
A4
A5
A6
A7
A12
A14
NC
VCC
NC
WE
A13
A8
A9
A11
OE
X28HC256
21
13
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3859 ILL F22
3859 FHD F03
3859 FHD F02
漏Xicor, Inc. 1991, 1995 Patents Pending
3859-2.7 3/27/96 T0/C2/D1 NS
1
Characteristics subject to change without notice