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X25256S8 Datasheet

  • X25256S8

  • IC-SMD-256K EEPROM

  • 17頁

  • ETC

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Preliminary Information
256K
X25256
5MHz SPI Serial E
2
PROM with Block Lock
鈩?/div>
Protection
鈥?Packages
鈥?-lead XBGA
鈥?-lead SOIC (JEDEC, EIAJ)
鈥?0-lead TSSOP
DESCRIPTION
32K x 8 Bit
FEATURES
鈥?5MHz Clock Rate
鈥?Low Power CMOS
鈥?lt;1碌A(chǔ) standby current
鈥?lt;5mA active current
鈥?2.5V To 5.5V Power Supply
鈥?SPI Modes (0,0 & 1,1)
鈥?32K X 8 Bits
鈥?4 byte page mode
鈥?Block Lock
鈩?/div>
Protection
鈥擯rotect 鏗乺st page, 鏗乺st 2 pages, 鏗乺st 4 pages,
鏗乺st 8 pages, 1/4, 1/2 or all of E
2
PROM array
鈥?Programmable Hardware Write Protection
鈥擨n-circuit programmable ROM mode
鈥?Built-In Inadvertent Write Protection
鈥擯ower-up/down protection circuitry
鈥擶rite enable latch
鈥擶rite protect pin
鈥?Self-Timed Write Cycle
鈥?ms write cycle time (typical)
鈥?High Reliability
鈥擡ndurance: 100,000 cycles
鈥擠ata Retention: 100 Years
鈥擡SD protection: 2000V on all pins
The X25256 is a CMOS 256K-bit serial E
2
PROM, inter-
nally organized as 32K x 8. The X25256 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25256 also features two additional inputs that
provide the end user with added 鏗俥xibility. By asserting
the HOLD input, the X25256 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire
input to the X25256 disabling all write attempts to the
status register, thus providing a mechanism for limiting
end user capability of altering 鏗乺st page, 鏗乺st 2 pages, 4
pages, 8 pages, 0, 1/4, 1/2 or all of the memory.
FUNCTIONAL DIAGRAM
Status
Register
Write
Protect
Logic
128
SO
SI
SCK
CS
HOLD
Command
Decode
And
Control
Logic
32K Byte
Array
128 X 512
X-Decode
Protect
Logic
128
128 X 512
248
4
Write
Control
And
Timing
Logic
2
1
1
64
248 X 512
4 X 512
2 X 512
1 X 512
1 X 512
8
Y Decode
Data Register
256 X 512
WP
Direct Write
鈩?/div>
and Block Lock
鈩?/div>
Protection is a trademark of Xicor, Inc.
REV 1.02 11/28/00
www.xicor.com
Characteristics subject to change without notice.
1 of 17

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    ICMIC [IC ...
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