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X25128Z-2.7 Datasheet

  • X25128Z-2.7

  • SPI Serial EEPROM

  • 14頁

  • ETC

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A
PPLICATION
N
OTE
A VA I L A B L E
AN61
Preliminary Information
Recommended System Management
Alternative: X5563
128K
X25128
SPI Serial EEPROM with Block Lock
鈩?/div>
Protection
DESCRIPTION
16K x 8 Bit
FEATURES
鈥?2MHz clock rate
鈥?SPI modes (0,0 & 1,1)
鈥?16K X 8 bits
鈥?2-byte page mode
鈥?Low Power CMOS
鈥?lt;1碌A standby current
鈥?lt;5mA active current
鈥?2.7V To 5.5V power supply
鈥?Block lock protection
鈥擯rotect 1/4, 1/2 or all of EEPROM array
鈥?Built-in inadvertent write protection
鈥擯ower-up/power-down protection circuitry
鈥擶rite enable latch
鈥擶rite protect pin
鈥?Self-timed write cycle
鈥?ms write cycle time (typical)
鈥?High reliability
鈥擡ndurance: 1 million cycles
鈥擠ata retention: 100 years
鈥擡SD protection: 2000V on all pins
鈥?Packages
鈥?-Lead XBGA
鈥?4-lead SOIC
The X25128 is a CMOS 131,072-bit serial EEPROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software proto-
col, allowing operation on a simple three-wire bus. The
bus signals are a clock input (SCK) plus separate data
in (SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25128 also features two additional inputs that
provide the end user with added 鏗俥xibility. By asserting
the HOLD input, the X25128 will ignore transitions on
its inputs, thus allowing the host to service higher pri-
ority interrupts. The WP input can be used as a hard-
wire input to the X25128 disabling all write attempts to
the status register, thus providing a mechanism for lim-
iting end user capability of altering 0, 1/4, 1/2 or all of
the memory.
The X25128 utilizes Xicor鈥檚 proprietary Direct Write
鈩?/div>
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
Status
Register
Write
Protect
Logic
X Decode
Logic
128
SO
SI
SCK
CS
HOLD
Command
Decode
and
Control
Logic
16K Byte
Array
16 X 256
128
16 X 256
256
32 X 256
WP
Write
Control
and
Timing
Logic
32
8
Y Decode
Data Register
REV 1.1 9/8/00
www.xicor.com
Characteristics subject to change without notice.
1 of 14

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