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WF256K16-XCX5 Datasheet

  • WF256K16-XCX5

  • Flash MCP

  • 11頁(yè)

  • ETC

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WF128K16, WF256K16-XCX5
5V FLASH MODULE
FEATURES
s
Access Times of 50, 60, 70, 90, 120 and 150ns
s
40 pin Ceramic DIP (Package 303)
s
Organized as 128Kx16 and 256Kx16
s
Sector Architecture
鈥?8 equal size sectors of 16KBytes each per chip
鈥?Any combination of sectors can be concurrently erased.
Also supports full chip erase
s
100,000 Erase/Program Cycles Minimum (0擄C to 70擄C)
s
Data Retention, 10 Years at 125擄C
s
Commercial, Industrial and Military Temperature Ranges
s
5 Volt Programming; 5V
鹵10%
Supply
s
Low Power CMOS
s
Embedded Erase and Program Algorithms
s
TTL Compatible Inputs and CMOS Outputs
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Page Program Operation and Internal Program Control Time
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
PRELIMINARY *
FIG. 1
PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
CS2*/NC
CS1
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
PIN DESCRIPTION
V
CC
WE
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
0
-
16
I/O
0-15
CS
1
-
2
OE
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
7
BLOCK DIAGRAM
FOR WF256K16-XCX5
I/O
0-7
WE
OE
A
0-16
I/O
8-15
FLASH MODULES
*
CS
2
for 256Kx16 and NC for 128Kx16
BLOCK DIAGRAM
FOR WF128K16-XCX5
I/O
0-7
WE
OE
A
0-16
I/O
8-15
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
CS
1
(1)
CS
2
(1)
CS
1
NOTE:
1. CS
1
and CS
2
are used to select the lower and upper 128Kx16 of the
device. CS
1
and CS
2
must not be enabled at the same time.
October 1998
1
White Microelectronics 鈥?Phoenix, AZ 鈥?(602) 437-1520

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