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WEDPN8M72V-XBX Datasheet

  • WEDPN8M72V-XBX

  • SDRAM MCP

  • 189.65KB

  • 15頁(yè)

  • ETC

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WEDPN8M72V-XBX
8Mx72 Synchronous DRAM
FEATURES
!
High Frequency = 100, 125MHz
!
Package:
鈥?219 Plastic Ball Grid Array (PBGA), 32 x 25mm
!
Single 3.3V 鹵0.3V power supply
!
Fully Synchronous; all signals registered on positive
edge of system clock cycle
!
Internal pipelined operation; column address can be
changed every clock cycle
!
Internal banks for hiding row access/precharge
!
Programmable Burst length 1,2,4,8 or full page
!
4096 refresh cycles
!
Commercial, Industrial and Military Temperature Ranges
!
Organized as 8M x 72
!
Weight: WEDPN8M72V-XBX - 2.5 grams typical
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access ,memory using 5 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip鈥檚 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is com-
patible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
BENEFITS
!
40% SPACE SAVINGS
!
Reduced part count
!
Reduced I/O count
鈥?19% I/O Reduction
!
Lower inductance and capacitance for low noise
performance
!
Suitable for hi-reliability applications
!
Upgradeable to 16M x 72 density (contact factory for
information)
* This product subject to change without notice.
Discrete Approach
11.9
11.9
11.9
11.9
11.9
ACTUAL SIZE
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
25
White Electronic Designs
WEDPN8M72V-XBX
32
S
A
V
I
N
G
S
40%
19%
Area
I/O
Count
November 2003 Rev. 13
5 x 265mm
2
= 1328mm
2
5 x 54 pins = 270 pins
1
800mm
2
219 Balls
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com

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