WEDPN8M64VR-XBX
8Mx64 Registered Synchronous DRAM
FEATURES
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Registered for enhanced performance of bus speeds
of 66 MHz and 100 MHz
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Package:
鈥?219 Plastic Ball Grid Array (PBGA), 32 x 25mm
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Single 3.3V 鹵0.3V power supply
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Fully synchronous; all signals registered on positive edge
of system clock cycle
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Internal pipelined operation; column address can be
changed every clock cycle
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Internal banks for hiding row access/precharge
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Programmable Burst length 1,2,4,8 or full page
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4096 refresh cycles
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Commercial, Industrial and Military Temperature Ranges
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Organized as 8M x 64
鈥?User configurable as 2x8Mx32 or 4x8Mx16
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Weight: WEDPN8M64VR-XBX - 2.5 grams typical
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access memory using 4 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip鈥檚 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits. The MCP also incorporates two
16-bit universal bus drivers for input control signals and ad-
dress.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is com-
patible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability
to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.
BENEFITS
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41% SPACE SAVINGS
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Reduced part count
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Reduced trace lengths for lower parasitic capacitance
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Glueless connection to memory controller/PCI bridge
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Laminate interposer for optimum TCE match
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Suitable for hi-reliability applications
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Upgradeable to 16M x 64 density (contact factory for
information)
* This data sheet describes a product that is subject to change without notice.
November 2003 Rev. 4
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White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com
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