音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

WEDPN8M64V-XBX Datasheet

  • WEDPN8M64V-XBX

  • SDRAM MCP

  • 12頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

WEDPN8M64V-XBX
8Mx64 Synchronous DRAM
FEATURES
鈻?/div>
High Frequency = 100, 125, 133**MHz
鈻?/div>
Package:
鈥?219 Plastic Ball Grid Array (PBGA), 25 x 25mm
鈻?/div>
Single 3.3V 鹵0.3V power supply
鈻?/div>
Unbuffered
鈻?/div>
Fully synchronous; all signals registered on positive
edge of system clock cycle
鈻?/div>
Internal pipelined operation; column address can be
changed every clock cycle
鈻?/div>
Internal banks for hiding row access/precharge
鈻?/div>
Programmable Burst length 1,2,4,8 or full page
鈻?/div>
4,096 refresh cycles
鈻?/div>
Commercial, Industrial and Military Temperature Ranges
鈻?/div>
Organized as 8M x 64
鈥?User Configurable as 2 x 8M x 32 or 4 x 8M x 16
鈻?/div>
Weight: WEDPN8M64V-XBX - 2.5 grams typical
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access memory using 4 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip鈥檚 33,554,432-bit banks is organized as 4,096 rows
by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA
0
, BA
1
select the bank; A
0-11
select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architec-
ture to achieve high-speed operation. This architecture is
compatible with the 2
n
rule of prefetch architectures, but
it also allows the column address to be changed on ev-
ery clock cycle to achieve a high-speed, fully random ac-
cess. Precharging one bank while accessing one of the
other three banks will hide the precharge cycles and pro-
vide seamless, high-speed, random-access operation.
BENEFITS
鈻?/div>
41% SPACE SAVINGS
鈻?/div>
Reduced part count
鈻?/div>
Low Profile: 2.20 mm (0.087) Max
鈻?/div>
Reduced trace lengths for lower parasitic capacitance
鈻?/div>
Laminate interposer for optimum TCE match
鈻?/div>
Suitable for hi-reliability applications
鈻?/div>
Upgradeable to 16M x 64 density (WEDPN16M64V-XBX)
*
This product is subject to change without notice.
** 133MHz available at commercial (0
o
C to + 70
o
C) temperature only.
Discrete Approach
11.9
ACTUAL SIZE
25
22.3
25
S
A
V
I
N
G
S
41%
Area
4 x 265mm
2
= 1061mm
2
625mm
2
November 2003 Rev. 13
1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com

WEDPN8M64V-XBX相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！