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WED48S8030E Datasheet

  • WED48S8030E

  • Industrial SDRAM

  • 26頁

  • ETC

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WED48S8030E
DRAM
2M x 8 Bits x 4 Banks Synchronous DRAM
FEATURES
DESCRIPTION
n
Single 3.3V power supply
n
Fully Synchronous to positive Clock Edge
n
Clock Frequency = 125, 100MHz
n
SDRAM CAS Latency = 2
n
Burst Operation
鈥equential or Interleave
鈥urst length = programmable 1,2,4,8 or full page
鈥urst Read and Write
鈥ultiple Burst Read and Single Write
n
The WED48S8030E is 67,108,864 bits of synchronous high
data rate DRAM organized as 4 x 2,097,152 words x 8 bits.
Synchronous design allows precise cycle control with the
use of system clock, I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Available in a 54 pin TSOP type II package the WED48S8030E
is tested over the industrial temp range (-40C to +85C) pro-
viding a solution for rugged main memory applications.
DATA Mask Control
鈥?096 refresh cycles across 64ms
n
Auto Refresh (CBR) and Self Refresh
n
Automatic and Controlled Precharge Commands
n
Suspend Mode and Power Down Mode
n
Industrial Temperature Range
FIG. 1
P
IN
C
ONFIGURATION
P
IN
D
ESCRIPTION
A
0-11
BA
0
, BA
1
CE
WE
CLK
CKE
DQ
0-7
DQM
RAS
CAS
V
DD
V
DDQ
V
SS
V
SSQ
NC
Address Inputs
Bank Select Addresses
Chip Select
Write Enable
Clock Input
Clock Enable
Data Input/Output
Data Input/Output Mask
Row Address Strobe
Column Address Strobe
Power (3.3V)
Data Output Power
Ground
Data Output Ground
No Connection
February 2002 Rev. 2
ECO #14194
1
White Electronic Designs Corporation 鈥?(508) 366-5151鈥?www.whiteedc.com

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