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WED2ZLRSP01S-BC Datasheet

  • WED2ZLRSP01S-BC

  • NBL SSRAM MCP

  • 13頁

  • ETC

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WED2ZLRSP01S
512K x 32/256K x 32 Dual Array
Synchronous Pipeline Burst NBL SRAM
FEATURES
n
n
n
n
n
n
n
Fast clock speed: 166, 150, 133, and 100MHz
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Single +2.5V 鹵 5% power supply (VDD)
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data I/Os
and control signals
DESCRIPTION
The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM
device employs high-speed, Low-Power CMOS silicon and
is fabricated using an advanced CMOS process. WEDC鈥檚
24Mb, Sync Burst SRAM MCP integrates two totally inde-
pendent arrays, the first organized as a 512K x 32, and the
second a 256K x 32.
All Synchronous inputs pass through registers controlled
by a positive edge triggered, single clock input per array.
The NBL or No Bus Latency Memory provides 100% bus
utilizaton, with no loss of cycles caused by change in modal
operation (Write to Read/Read to Write). All inputs except
for Asynchronous Output Enable and Burst Mode control
are synchronized on the positive or rising edge of Clock.
Burst order control must be tied either HIGH or LOW, Write
cycles are internally self-timed, and writes are initiated on
the rising edge of clock. This feature eliminates the need
for complex off-chip write pulse generation and proved
increased timing flexibility for incoming signals.
n
Burst control (interleaved or linear burst)
n
Packaging:
鈥?209-bump BGA package
n
Low capacitive bus loading
FIG. 1 PIN CONFIGURATION
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1
V
SS
NC
A_ADR
A_ADR
A_ADR
A_ADR
A_ADR
NC
V
SS
V
SS
V
SS
NC
B_ADR
B_ADR
B_ADR
B_ADR
B_ADR
NC
V
SS
2
A_DAT
B
0
A_DAT
B
4
A_ADR
V
SS
A_CLK
V
SS
A_ADR
A_DAT
C
0
A_DAT
C
4
V
SS
B_DAT
B
0
B_DAT
B
4
B_ADR
V
SS
B_CLK
V
SS
NC
B_DAT
C
4
B_DAT
C
0
3
A_DAT
B
1
A_DAT
B
5
A_OE
A_CKE
A_GWE
A_CS
2
A_CS
1
A_DAT
C
1
A_DAT
C
5
V
SS
B_DAT
B
1
B_DAT
B
5
B_OE
B_CKE
B_GWE
B_CS
2
B_CS
1
B_DAT
C
5
B_DAT
C
1
4
A_DAT
B
2
A_DAT
B
6
A_ADV
V
CC
V
CC
V
CC
A_CS
2
A_DAT
C
2
A_DAT
C
6
V
SS
B_DAT
B
2
B_DAT
B
6
B_ADV
V
CC
V
CC
V
CC
B_CS
2
B_DAT
C
6
B_DAT
C
2
5
A_DAT
B
3
A_DAT
B
7
A_BWE
B
V
CC
V
CC
V
CC
A_BWE
C
A_DAT
C
3
A_DAT
C
7
V
SS
B_DAT
3
B_DAT
7
B_BWE
B
V
CC
V
CC
V
CC
B_BWE
c
B_DAT
C
7
B_DAT
C
3
6
V
SS
V
SS
V
SS
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
7
A_DAT
A
0
A_DAT
A
4
A_BWE
A
V
CC
V
CC
V
CC
A_BWE
D
A_DAT
D
0
A_DAT
D
4
V
SS
B_DAT
A
0
B_DAT
A
4
B_BWE
A
V
CC
V
CC
V
CC
B_BWE
D
B_DAT
D
4
B_DAT
D
0
8
A_DAT
A
1
A_DAT
A
5
A_ZZ
V
CC
V
CC
V
CC
A_LBO
A_DAT
D
1
A_DAT
D
5
V
SS
B_DAT
A
1
B_DAT
A
5
B_ZZ
V
CC
V
CC
V
CC
B_LBO
B_DAT
D
5
B_DAT
D
1
9
A_DAT
A
2
A_DAT
A
6
A_ADR
V
CC
V
CC
V
CC
A_ADR
A_DAT
D
2
A_DAT
D
6
V
SS
B_DAT
A
2
B_DAT
A
6
B_ADR
V
CC
V
CC
V
CC
B_ADR
B_DAT
D
6
B_DAT
D
2
10
A_DAT
A
3
A_DAT
A
7
A_ADR
A_ADR
A_ADR
1
A_ADR
A_ADR
A_DAT
D
3
A_DAT
D
7
V
SS
B_DAT
A
3
B_DAT
A
7
B_ADR
B_ADR
B_ADR
1
B_ADR
B_ADR
B_DAT
D
7
B_DAT
D
3
11
V
SS
NC
A_ADR
A_ADR
A_ADR
0
A_ADR
A_ADR
NC
V
SS
V
SS
V
SS
NC
B_ADR
B_ADR
B_ADR
0
B_ADR
B_ADR
NC
V
SS
April 2002 Rev. 0
ECO #15203
1
White Electronic Designs Corporation 鈥?(502) 366-5151鈥?www.whiteedc.com

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