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WED2ZL362MS Datasheet

  • WED2ZL362MS

  • NBL SSRAM MCP

  • 273.80KB

  • 12頁

  • ETC

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White Electronic Designs
WED2ZL362MS
72Mb, 2M x 36 Synchronous Pipeline Burst NBL SRAM
FEATURES
n
n
n
n
n
n
n
Fast clock speed: 225, 200, 166 and 150MHz
Fast access times: 2.8, 3.0, 3.5 and 3.8ns
Fast OE access times: 2.8, 3.0, 3.5 and 3.8ns
Separate Core and I/O Power Supply
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data I/Os
and control signals
Advanced
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated us-
ing an advanced CMOS process. WEDC聮s 72Mb
SyncBurst SRAMs integrate two 2M x 18 SRAMs into a
single BGA package to provide a 2M x 36 configuration.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK). The
NBL or No Bus Latency Memory utilizes all the band-
width in any combination of operating cycles. Address,
data inputs, and all control signals except output enable
and linear burst order are synchronized to input clock.
Burst order control must be tied 聯(lián)High or Low.聰 Asyn-
chronous inputs include the sleep mode enable (ZZ)
and Output Enable (OE). Write cycles are internally
self-timed and initiated by the rising edge of the clock
input. This feature eliminates complex off-chip write
pulse generation and provides increased timing flex-
ibility for incoming signals.
n
Burst control (interleaved or linear burst)
n
Packaging:
聲 119-bump BGA package
n
Low capacitive bus loading
FIG. 1 PIN CONFIGURATION
(TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
SA
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
SA
CE
2
SA
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
SA
SA
RFU
3
SA
SA
SA
V
SS
V
SS
V
SS
BW
C
V
SS
NC
V
SS
BW
D
V
SS
V
SS
V
SS
LBO
SA
RFU
4
SA
ADV
V
DD
NC
CE
1
OE
SA
WE
V
DD
CLK
NC
CKE
SA
1
SA
0
V
DD
SA
RFU
5
SA
SA
SA
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
SA
RFU
6
SA
CE
2
SA
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
SA
NC
NC
7
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
BW
C
BW
D
BW
A
BW
B
BLOCK DIAGRAM
2M x 18
CLK
CKE
ADV
LBO
CE1
CE2
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
2M x 18
Address Bus
(SA
0
鈥?SA
20
)
DQ
C
, DQ
D
DQP
C
, DQP
D
DQ
A
, DQ
B
DQP
A
, DQP
B
DQ
A
鈥?/div>
DQ
D
DQP
A
鈥?/div>
DQP
D
July 2002 Rev. 0
ECO # 15238
1
White Electronic Designs Corporation 聲 (508) 366-5151 聲 www.whiteedc.com

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