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WED2ZL361MS-BC Datasheet

  • WED2ZL361MS-BC

  • NBL SSRAM MCP

  • 340.55KB

  • 12頁

  • ETC

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White Electronic Designs
WED2ZL361MS
1Mx36 Synchronous Pipeline Burst NBL SRAM
FEATURES
n
Fast clock speed: 250, 225, 200, 166, 150, 133MHz
n
Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns
n
Fast OE access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns
n
Separate +2.5V 鹵 5% power supplies for Core, I/O
(V
DD
, V
DDQ
)
n
Snooze Mode for reduced-standby power
n
Individual Byte Write control
n
Clock-controlled and registered addresses, data
I/Os and control signals
n
Burst control (interleaved or linear burst)
n
Packaging:
聲 119-bump BGA package
n
Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC聮s 32Mb
SyncBurst SRAMs integrate two 1M x 18 SRAMs into a
single BGA package to provide 1M x 36 configuration. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The NBL or No Bus Latency Memory utilizes all the band-
width in any combination of operating cycles. Address,
data inputs, and all control signals except output en-
able and linear burst order are synchronized to input
clock. Burst order control must be tied 聯(lián)High or Low.聰
Asynchronous inputs include the sleep mode enable
(ZZ). Output Enable controls the outputs at any given
time. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature elimi-
nates complex off-chip write pulse generation and pro-
vides increased timing flexibility for incoming signals.
NOTE: NBL (No Bus Latency) is equivalent to ZBT聶
FIG. 1
P
IN
C
ONFIGURATION
(TOP VIEW)
B
LOCK
D
IAGRAM
5
SA
SA
SA
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
SA
NC
6
SA
CE2
SA
DQP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
SA
NC
NC
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
Address Bus
(SA
0
SA
19
)
1M x 18
CLK
CKE
ADV
LBO
CE1
CE2
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
SA
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
2
SA
CE2
SA
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
SA
NC
NC
3
SA
SA
SA
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
LBO
SA
NC
4
SA
ADV
V
DD
NC
CE1
OE
SA
WE
V
DD
CLK
NC
CKE
SA1
SA0
V
DD
SA
NC
BWc
BWd
1M x 18
BWa
BWb
-
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
DQa
DQPa
-
DQd
-
DQPd
October 2002 Rev. 5
ECO # 15466
1
White Electronic Designs Corporation 聲 (508) 366-5151 聲 www.whiteedc.com

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