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WED2ZL236512S-BC Datasheet

  • WED2ZL236512S-BC

  • NBL SSRAM MCP

  • 12頁

  • ETC

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White Electronic Designs
WED2ZL236512S
SRAM
2 x 512K x 36 Synchronous Pipeline Burst NBL SRAM
FEATURES
FEATURES
!
Fast clock speed: 166, 150, 133, and 100MHz
!
Fast access times: 3.5ns, 3.8ns, 4.0ns, and 5.0ns
!
Fast OE access times: 3.5ns, 3.8ns, 4.0ns, and 5.0ns
!
Single +2.5V 鹵 5% power supply (VDD)
!
Snooze Mode for reduced-standby power
!
Individual Byte Write control
!
Clock-controlled and registered addresses, data I/Os
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an ad-
vanced CMOS process. WEDC鈥檚 32Mb SyncBurst SRAMs
integrate two 512K x 36 SRAMs into a single BGA package
to provide 2 x 512K x 36 configuration. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single-clock input (CLK). The NBL or No Bus La-
tency Memory utilizes all the bandwidth in any combination
of operating cycles. Address, data inputs, and all control
signals except output enable and linear burst order are syn-
chronized to input clock. Burst order control must be tied
鈥淗igh or Low.鈥?Asynchronous inputs include the sleep mode
enable (ZZ). Output Enable controls the outputs at any
given time. Write cycles are internally self-timed and initi-
ated by the rising edge of the clock input. This feature elimi-
nates complex off-chip write pulse generation and pro-
vides increased timing flexibility for incoming signals.
and control signals
!
Burst control (interleaved or linear burst)
鈥?119-bump BGA package
!
Packaging:
!
Low capacitive bus loading
FIG. 1
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
DD
SA
NC
DQ
C
DQ
C
V
DD
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
V
DD
DQ
D
DQ
D
DNC
DNC
2
CONFIGURA
PIN CONFIGUR ATION
(TOP VIEW)
3
SA
SA
SA
V
SS
V
SS
V
SS
BW
C
V
SS
DNC
V
SS
BW
D
V
SS
V
SS
V
SS
LBO
SA
4
SA
ADV
V
DD
DNC
DNC
OE
DNC
WE
V
DD
CLK
NC
CKE
SA
1
SA
0
V
DD
SA
5
SA
SA
SA
V
SS
V
SS
V
SS
BW
B
V
SS
DNC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
SA
6
SA
CE
B
SA
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
SA
NC
7
V
DD
DNC
DNC
DQ
B
DQ
B
V
DD
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
V
DD
DQ
A
DQ
A
NC
ZZ
CEb
CLK
CKE
SA
ADV
OE
WE
BWa
BWb
BWc
BWd
LBO
ZZ
CEa
DQ
a
-
DQ
d
DQPa
-
DQP
d
BLOCK DIAGR
GRAM
BLOCK DIAGR AM
SA
CE
A
SA
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
SA
NC
512K x 36
SSRAM
512K x 36
SSRAM
V
DD
NC
NC
NC
NC
NC
VDD
U
Note:
DNC = Do Not Connect. Connections to these pins may cause the device to not function properly.
January 2002, Rev. 4
ECO #14644
1
White Electronic Designs Corporation 鈥?(508) 366-5151 鈥?www.whiteedc.com

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