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WED2DL36513V-B Datasheet

  • WED2DL36513V-B

  • SSRAM MCP

  • 10頁

  • ETC

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White Electronic Designs
FEATURES
鈻?/div>
Fast clock speed: 200, 166, 150 & 133MHz
鈻?/div>
Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
鈻?/div>
Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
鈻?/div>
Available with 1.5ns setup and 0.5ns hold times or
1.0ns setup and hold times.
鈻?/div>
Single +3.3V power supply (V
DD
)
鈻?/div>
Seperate +3.3V or +2.5V isolated output buffer
supply (V
DDQ
)
鈻?/div>
Snooze Mode for reduced-power standby
鈻?/div>
Single-cycle deselect
鈻?/div>
Common data inputs and data outputs
鈻?/div>
Individual Byte Write control and Global Write
鈻?/div>
Clock-controlled and registered addresses, data
I/Os and control signals
鈻?/div>
Burst control (interleaved or linear burst)
鈻?/div>
Packaging:
聲 119-bump BGA package
鈻?/div>
Low capacitive bus loading
鈻?/div>
IEEE 1149.1 JTAG Compatible Boundary Scan
WED2DL36513V
512Kx36 Synchronous Pipeline Burst SRAM
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC聮s 16Mb
SyncBurst SRAMs integrate two 512K x 18 SRAMs into
a single BGA package to provide 512K x 36 configura-
tion. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single-clock input
(CLK). The synchronous inputs include all addresses, all
data inputs, active LOW chip enable (CE), burst control
inputs (ADSC, ADSP, ADV), byte write enables (BW
0-3
)
and global write (GW). Asynchronous inputs include the
output enable (OE), clock (CLK) and snooze enable (ZZ).
There is also a burst mode input (MODE) that selects
between interleaved and linear burst modes. Write Cycles
can be from one to four bytes wide, as controlled by the
write control inputs. Burst operation can be initiated with
either address status processor (ADSP) or address sta-
tus controller (ADSC) inputs. Subsequent burst ad-
dresses can be internally generated as controlled by the
burst advance input (ADV).
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
FIG. 1
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
SA
SA
SA
P
IN
C
ONFIGURATION
(TOP VIEW)
3
SA
SA
SA
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
SA
TDI
4
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
SA1
SA0
V
DD
SA
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
NC
SA
TDO
6
SA
SA
SA
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
SA
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
BW
c
BW
d
GW
ADV
SA
CLK
ADSP
ADSC
OE
BWE
CE
MODE
ZZ
BW
a
BW
b
B
LOCK
D
IAGRAM
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
SA
NC
TMD
512K x 18
SSRAM
DQ
a
,
DQP
a
DQ
b
,
DQP
b
512K x 18
SSRAM
DQ
c
,
DQP
c
DQ
d
,
DQP
d
* Enable on pins C7 and R7 are options for the three CE density only.
July 2002 Rev. 3
ECO #14637
1
White Electronic Designs Corporation 聲 (508) 366-5151 聲 www.whiteedc.com

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