L鈩?/div>
Preliminary
WCMA4016U1X
256K x 16 Static RAM
Features
鈥?Low voltage range: 2.7V鈥?.6V
鈥?Ultra-low active, standby power
鈥?Easy memory expansion with CE
1
and CE
2
and OE fea-
tures
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
18
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table at the back of this
datasheet for a complete description of read and write modes.
Functional Description
[1]
The WCMA4016U1X is a high-performance CMOS static
RAM organized as 262,144 words by 16 bits. This device
features advanced circuit design to provide ultra-low active
current and standby current. This is ideal for providing more
battery life in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99% when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or
Logic Block Diagram
1
BLE
DATA IN DRIVERS
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
8
ROW DECODER
I/O
9
V
SS
I/O
0
鈥?I/O
7
I/O
8
鈥?I/O
15
V
CC
Pin Configurations
FBGA (Top View)
2
OE
BHE
I/O
10
I/O
11
I/O
12
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
256K 脳 16
RAM Array
2048 脳 2048
SENSE AMPS
I/O
14
I/O
13
I/O
15
COLUMN DECODER
NC
BHE
WE
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
OE
BLE
BHE
BLE
NC
A
8
CE
2
CE
1
Pow
-
er Down
Circuit
CE
2
CE
1
.
Weida Semiconductor, Inc.
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