WB1330
Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers
Features
鈥?Operating voltage 2.7V to 5.5V
鈥?PLL1 operating frequency:
鈥?2.5 GHz with prescaler ratios of 32/33 and 64/65
鈥?PLL2 operating frequency:
鈥?600 MHz with prescaler ratios of 8/9 and 16/17
鈥?Lock detect feature
鈥?Power-down mode I
CC
< 1
碌A
typical at 3.0V
鈥?20-pin TSSOP (Thin Shrink Small Outline Package)
Applications
The Cypress WB1330 is a dual serial input PLL frequency
synthesizer designed to combine the RF and IF mixer frequen-
cy sections of wireless communications systems. One 2.5-
GHz and one 600-MHz prescaler, each with pulse swallow ca-
pability are included. The device operates from 2.7V and dis-
sipates only 30 mW. (See
Figure 1
for an example application
diagram of the WB1330.)
WB1330 Dual Hi-Lo PLL Block Diagram
GND (4)
GND (7)
V
CC
1 (1)
V
CC
2 (20)
V
P
1 (2)
F
IN
1 (5)
F
IN
1# (6)
Prescaler
32/33 or
64/65
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp1
Phase
Detector
Charge
Pump
D
O
PLL1 (3)
19-Bit
Latch
OSC_IN (8)
Pwr-dwn
PLL1
fr1
fr fp
Monitor
Output
Selector
15-Bit
Reference Counter
Latch
Selector
LE (13)
DATA (12)
CLOCK (11)
20-Bit Latch
20-Bit Latch
15-Bit
Reference Counter
19-Bit
Latch
Pwr-dwn
PLL2
F
O
/LD (10)
fr2
Cntrl 22-Bit
Shift
Reg.
Power
Control
F
IN
2 (16)
F
IN
2# (15)
Prescaler
8/9 or
16/17
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Phase
Detector
fp2
Charge
Pump
D
O
PLL2 (18)
GND (14)
GND (9)
GND (17)
V
P
2 (19)
Pin Configuration
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
GND
F
O
/LD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
August 11, 2000, rev. *B
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