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W981208BH Datasheet

  • W981208BH

  • 4M x 4 BANKS x 8 BIT SDRAM

  • 1493.54KB

  • 41頁

  • WINBOND

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W981208BH
4M
脳
4 BANKS
脳
8 BIT SDRAM
GENERAL DESCRIPTION
W981208BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
4M words
脳
4 banks
脳
8 bits. Using pipelined architecture and 0.175
碌
m process technology,
W981208BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W981208BH is sorted into three speed grades: -7, -75 and -
8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the
PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981208BH is ideal for main memory in
high performance applications.
FEATURES
鈥?/div>
3.3V
鹵
0.3V Power Supply
鈥?/div>
Up to 143 MHz Clock Frequency
鈥?/div>
4,194,304 Words
脳
4 banks
脳
8 bits organization
鈥?/div>
Auto Refresh and Self Refresh
鈥?/div>
CAS Latency: 2 and 3
鈥?/div>
Burst Length: 1, 2, 4, 8, and full page
鈥?/div>
Burst Read, Single Writes Mode
鈥?/div>
Byte Data Controlled by DQM
鈥?/div>
Power-Down Mode
鈥?/div>
Auto-Precharge and Controlled Precharge
鈥?/div>
4K Refresh cycles /64 mS
鈥?/div>
Interface: LVTTL
鈥?/div>
Packaged in TSOP II 54 pin, 400 mil - 0.80
KEY PARAMETERS
SYM.
DESCRIPTION
MIN.
/MAX.
-7
(PC133, CL2)
-75
(PC133, CL3)
-8H
(PC100)
t
CK
t
AC
t
RP
t
RCD
I
CC1
I
CC4
I
CC6
Clock Cycle Time
Access Time from CLK
Precharge to Active Command
Active to Read/Write Command
Operation Current (Single bank)
Burst Operation Current
Self-refresh Current
Min.
Max.
Min.
Min.
Max.
Max.
Max.
7 nS
5.4 nS
15 nS
15 nS
80 mA
100 mA
2 mA
7.5 nS
5.4 nS
20 nS
20 nS
75 mA
95 mA
2 mA
8 nS
6 nS
20 nS
20 nS
70 mA
90 mA
2 mA
-1-
Publication Release Date: October 2000
Revision A1

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