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W946432AD Datasheet

  • W946432AD

  • 512K X 4 BANKS X 32 BITS DDR SDRAM

  • 40頁

  • WINBOND

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W946432AD
512K
脳
4 BANKS
脳
32 BITS DDR SDRAM
GENERAL DESCRIPTION
The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access
memory organized as 512K words x 4 banks x 32 bits.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for
WRITEs.
The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH
and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control
signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command are used to select the bank and row to
be accessed. The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. An
AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective bandwidth by hiding row precharge and
activation time.
FEATURES
鈥?/div>
Double-data-rate
architecture; two data transfers
鈥?/div>
Four
鈥?/div>
Data
鈥?/div>
Burst
鈥?/div>
CAS
internal banks for concurrent operation
mask (DM) for write data
lengths: 2, 4, or 8
Latency: 3
per clock cycle
鈥?/div>
Bidirectional,
data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
is edge-aligned with data for READs;
center-aligned with data for WRITEs
clock inputs (CLK and CLK )
鈥?/div>
DQS
鈥?/div>
AUTO
鈥?/div>
Auto
PRECHARGE option for each burst
access
Refresh and Self Refresh Modes
Maximum Average Periodic Refresh
Interval
(SSTL_2 compatible) I/O
= 2.5V 鹵 0.2V
= 2.5V 鹵 0.2V
鈥?/div>
Differential
鈥?/div>
DLL
aligns DQ and DQS transitions with CLK
transitions
DLL on or DLL off mode
鈥?/div>
15.6us
鈥?/div>
2.5V
鈥?/div>
Programmable
鈥?/div>
Commands entered on each positive CLK edge;
data and data mask referenced to both edges of
DQS
鈥?/div>
V
DD
Q
鈥?/div>
V
DD
PRELIMINARY DATA:9/8/00
1

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    512K X 4 BANKS X 32 BITS DDR SDRAM
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    512K X 4 BANKS X 32 BITS DDR SDRAM
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