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W942516AH Datasheet

  • W942516AH

  • 4M x 4 BANKS x 16 BIT DDR SDRAM

  • 26頁

  • WINBOND

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PRELIMINARY W942516AH
4M
脳
4 BANKS
脳
16 BIT DDR SDRAM
GENERAL DESCRIPTION
W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words
脳
4 banks
脳
16 bits. Using pipelined architecture and 0.175
碌m
process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7).
To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed
grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -
75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2
specification
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942516AH is ideal for main memory in
high performance applications.
FEATURES
鈥?/div>
2.5V
鹵
0.2V Power Supply
鈥?/div>
Up to 143 MHz Clock Frequency
鈥?/div>
Double Data Rate architecture; two data transfers per clock cycle
鈥?/div>
Differential clock inputs (CLK and CLK )
鈥?/div>
DQS is edge-aligned with data for Read; center-aligned with data for Write
鈥?/div>
CAS Latency: 2 and 2.5
鈥?/div>
Burst Length: 2, 4, and 8
鈥?/div>
Auto Refresh and Self Refresh
鈥?/div>
Precharged Power Down and Active Power-Down
鈥?/div>
Write Data Mask
鈥?/div>
Write Latency = 1
鈥?/div>
8K Refresh cycles / 64 mS
鈥?/div>
Interface: SSTL-2
鈥?/div>
Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch
KEY PARAMETERS
SYM.
DESCRIPTION
MIN.
/MAX.
-7
-75
-8
t
CK
t
RAS
t
RC
I
DD1
I
DD4
I
DD6
CL=2
CL=2.5
Active to Precharge Command Period
Active to Ref/Active Command Period
Operation Current (Single bank)
Burst Operation Current
Self-Refresh Current
Clock Cycle Time
min.
min.
min.
min.
max.
max.
max.
7.5 nS
7 nS
45 nS
65 nS
110mA
165mA
3mA
8 nS
7.5 nS
45 nS
65 nS
110mA
155mA
3mA
10 nS
8 nS
50 nS
70 nS
100mA
150mA
3mA
-1-
Publication Release Date: May 2001
Revision .0.0

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