鈥?/div>
Compatible with IEEE 802.3 10BASE2 and 10BASE5
CMOS process provides low power consumption
Mixed-mode circuit design integrates all transceiver electronics except signal and power isolation
and minimizes external component count
On-chip jabber timer and state machine meet the requirements for IEEE 802.3 MAU function
External selective SQE test function allows operation with IEEE 802.3 compatible repeater
Precision detection circuit design implements transmit mode collision detection
External selective jabber lockup function allows infinite data transmission
Standard 16-pin DIP and 28-pin PLCC package provide easy implementation of a MAU
PIN CONFIGURATIONS
D
I
+
4
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
5
6
7
8
9
10
11
C
S
O
-
3
C
S
O
+
2
C
L
S
T
X N
O C
R
X
I
CSO+
CSO-
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
ER-
DO+
DO-
V
SS
DI-
DI+
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLS
TXO
RXI
V
SS
ER-
ER+
V
DD
SQE
1 28 27 26
25
24
23
22
21
20
19
12 13 14 15 16 17 18
D
I
-
D
O
+
D
O
-
S
Q
E
V
D
D
V
D
D
E
R
+
-1-
Publication Release Date: September 1994
Revision A3