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W88112F Datasheet

  • W88112F

  • ATAPI CD-ROM DECODER & CONTROLLER

  • 459.60KB

  • 64頁

  • WINBOND

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W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
Table Of Contents
GENERAL DESCRIPTION ________________________________________________________________5
BLOCK DIAGRAM_______________________________________________________________________6
PIN CONFIGURATION ___________________________________________________________________7
PIN DESCRIPTIONS______________________________________________________________________8
REGISTERS DESCRIPTION______________________________________________________________12
IR - Index Register (read/write) ____________________________________________________________12
PFAR - Packet FIFO Access Register - (read 00h) _____________________________________________12
INTCTL - Interrupt Control Register - (write 01h) _____________________________________________12
INTREA - Interrupt Reason Register - (read 01h) ______________________________________________13
TBCL/TBCH - Transfer Byte/Word Counter - (read/write 02h/03h) ________________________________15
TACL/TACH - Transfer Address Counter - (write 04h/05h) ______________________________________15
TBL/TBH - Transfer Block Register - (read/write 24h/25h) ______________________________________15
THTRG - Transfer to Host Trigger Register - (write 06h)________________________________________15
TACK - Transfer Acknowledge - (write 07h) __________________________________________________16
HEAD0 to HEAD3 - Header Registers - (read 03h to 07h)_______________________________________16
BIAL/BIAH - Buffering Initial Address Register - (write 08h/09h) _________________________________16
BACL, BACH - Buffering Address Counter - (read 0Ah/0Bh)_____________________________________16
EIAL/EIAH - ECC Initial Address Register- (read 08h/09h, write 0Ch/0Dh)_________________________16
SCBL/SCBH - Subcode Block Register - (read/write 26h/27h) ____________________________________17
DDBL/DDBH - Decoded Data Block Register - (read/write 28h/29h) ______________________________17
CTRL0 - Control Register 0 - (write 0Ah) ____________________________________________________17
CTRL1 - Control Register 1 - (write 0Bh) ____________________________________________________18
STAT0 - Status Register 0 - (read 0Ch) ______________________________________________________19
STAT1 - Status Register 1 - (read 0Dh) ______________________________________________________20
DHTACK - DRAM to Host Transfer Acknowledge - (write 0Eh) __________________________________21
STAT2 - Status Register 2 - (read 0Eh) ______________________________________________________21
FRST - Firmware Reset Register - (write 0Fh) ________________________________________________22
-1-
Publication Release Date: Aug, 1996
Preliminary/Confidential Revision A0.1

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