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W83194R-67B Datasheet

  • W83194R-67B

  • 100MHZ 3-DIMM CLOCK FOR VIA MVP4

  • 18頁(yè)

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W83194R-67B
100MHZ 3-DIMM CLOCK FOR VIA MVP4
1.0 GENERAL DESCRIPTION
The W83194R-67B is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67B provides sixteen
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67B also
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194R-67B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
Spread spectrum built in at 鹵0.5% or 鹵0.25% to reduce EMI. Programmable stopping individual
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clock outputs and frequency selection through I C interface. The device meets the Pentium power-up
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50鹵 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
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Supports Pentium鈩?, AMD, Cyrix CPU with I C.
4 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 4ns propagation delay SDRAM from buffer input
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 60 MHz to 124 MHz CPU
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I C 2-Wire serial interface and I C read back
0~0.5% down type or 鹵0.25% or 鹵0.5% spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
2ms power up clock stable time
MODE pin for power Management
One 48 MHz for USB & one 24 MHz for super I/O
Packaged in 48-pin SSOP
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Publication Release Date: Dec. 1999
Revision 0.50

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