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Supports AMD CPU with I
2
C.
3 CPU clocks (one free-running chipset clock controlled by I2C)
13 SDRAM clocks for 3 DIMMs
6 PCI synchronous clocks
One IOAPIC clock for multiprocessor support
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
< 5ns propagation delay SDRAM from buffer input
Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 66 MHz to 200 MHz CPU
Stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio
Programmable skew and driving strength for CPU and SDRAM clock outputs
I
2
C 2-Wire serial interface and I
2
C read back
鹵0.25% or 鹵0.5% spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
MODE pin for power Management and RESET# out when system hang
One 48 MHz for USB & one 24 MHz for super I/O
48-pin SSOP package
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-1-
Publication Release Date: May 2000
Revision 0.42
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