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2 CPU clock outputs
One CPU/2 output as reference input to DRCG
3 3V66 clock outputs
3 IOAPIC clock outputs
8 PCI synchronous clocks.
Optional single or mixed supply:
(VddQ2 = VddQ3 = 3.3V or VddQ3=3.3V, VddQ2=2.5V)
CPU to 3V66 offset .0 to 1.5 ns
3V66 to PCI offset 1.5 to 4.0 ns
Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
Smooth frequency switch with selections from 66.8 to 200MHz
I
2
C 2-Wire serial interface and I
2
C read back
0.5% and 0.75% center type spread spectrum
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
48 MHz pins for USB
24 MHz for super I/O
48-pin SSOP package
-1-
Publication Release Date: Dec. 1999
Revision 0.40