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W83194BR-39B Datasheet

  • W83194BR-39B

  • STEP-LESS 3-DIMM CLOCK

  • 20頁

  • WINBOND

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W83194BR-39B
STEP-LESS 3-DIMM CLOCK
1.0 GENERAL DESCRIPTION
The W83194BR-39B is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-39B provides 64 CPU/PCI
frequencies which are selectable with smooth transitions by hardware or software. W83194BR-39B
also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194BR-39B provides step-less frequency programming by controlling the VCO freq. and the
programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the
RESET# pin will output 4ms pulse signal.
The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at
鹵0.5% or 鹵0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency
selection through I
2
C interface. The device meets the Pentium power-up stabilization, which requires
CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA,
PCI, CPU, DIMM) is not recommend.
2.0 PRODUCT FEATURES
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Supports Pentium鈩?II and !!! CPU with I
2
C.
2 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMMs
6 PCI synchronous clocks
One IOAPIC clock for multiprocessor support
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VddL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
< 5ns propagation delay SDRAM from buffer input
Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 66 MHz to 200 MHz CPU
Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio
I
2
C 2-Wire serial interface and I
2
C read back
鹵0.25% or 鹵0.5% spread spectrum function to reduce EMI in freq. table mode
Programmable spread spectrum in the M/N step-less mode
Programmable registers to enable/stop each output and select modes
MODE pin for power Management
RESET# out when watch dog timer time out
One 48 MHz for USB & one 24 MHz for super I/O
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-1-
Publication Release Date: June 2000
Revision 0.46

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