W532
Frequency Multiplying, Peak Reducing EMI Solution
Features
鈥?Cypress PREMIS鈩?family offering
鈥?Generates an EMI optimized clocking signal at the
output
鈥?Selectable frequency range and multiplication factor
鈥?Single 1.25% or 5% center spread output
鈥?Integrated loop filter components
鈥?Operates with a 3.3V or 5V supply
鈥?Low power CMOS design
鈥?Available in 16-pin SOIC
Table 1. Output Frequency Range Selection
OR2
0
0
1
1
OR1
0
1
0
1
Output Range
(Multiplication Factor Selection)
reserved
15 MHz
鈮?/div>
F
IN
鈮?/div>
30 MHz
30 MHz
鈮?/div>
F
IN
鈮?/div>
60 MHz
60 MHz
鈮?/div>
F
IN
鈮?/div>
120 MHz
Table 2. Modulation Width Selection
MW
0
1
Output
F
avg
+
0.625%
鈮?/div>
F
out
鈮?/div>
F
avg
鈥?0.625%
F
avg
+
2.5%
鈮?/div>
F
out
鈮?/div>
F
avg
鈥?2.5%
Key Specifications
Supply Voltages: ........................................V
DD
= 3.3V 鹵0.3V
or V
DD
= 5V 鹵10%
Frequency Range: .........................15 MHz
鈮?/div>
F
out
鈮?/div>
120 MHz
Cycle to Cycle Jitter: ......................................... 150 ps (typ.)
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time ................................... 5 ns (max.)
Table 3. Input Frequency Range Selection
IR2
0
0
1
1
IR1
0
1
0
1
Input Range
reserved
15 MHz
鈮?/div>
F
IN
鈮?/div>
30 MHz
30 MHz
鈮?/div>
F
IN
鈮?/div>
60 MHz
60 MHz
鈮?/div>
F
IN
鈮?/div>
120 MHz
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
X1
XTAL
Input
X2
W532
Spread Spectrum
Output
(EMI suppressed)
X1
X2
AVDD
*OR1
NC
AGND
^OR2
*SSON#
1
2
3
4
5
6
16
15
14
13
12
11
10
9
VDD
GND
IR1^
IR2^
SSOUT
GND
VDD
MW*
W532
7
8
3.3V or 5.0V
Oscillator or
Reference Input
X1
Notes:
1. ^ pins have internal pull-up
2. * pins have internal pull-down
W532
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor.
Cypress Semiconductor Corporation
Document #: 38-07253 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 28, 2002
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