Preliminary W45B512
512K
脳
1 SERIAL FLASH
GENERAL DESCRIPTION
The W45B512 is manufactured with Winbond鈥?high performance CMOS WinFlash technology. The
s
Serial Flash is organized as 16 sectors of 4096 Bytes for the W45B512. The memory is accessed for
Read or Erase/Program by the SPI bus compatible serial protocol. The bus signals are: serial data
input (SI), serial data output (SO), serial clock (SCK), write protect (#WP), chip enable (#CE), and
hardware reset (#RESET). This device is offered in 8L SON and 32L PLCC package.
FEATURES
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Single 2.7
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3.6V Read and Write Operations
Serial Interface Architecture
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SPI Compatible: Mode 0 and Mode 3
Byte Serial Read with Single Command
Superior Reliability
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Endurance: 10,000 Cycles (Typ.)
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20 years Data Retention
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Automatic Write Timing
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Internal V
PP
Generation
End-of-Write Detection
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Software Status
20 MHz Max Clock Frequency
Hardware Reset Pin (#RESET)
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Resets the device to Standby Mode
TTL Compatibility
Hardware Data Protection
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Protects/Unprotects the device from Write
operation
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Low Power Consumption
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Active Current: 30 mA (Max.)
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Standby Current: 15 碌A (Max.)
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Sector or Chip-erase Capability
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Uniform 4 KByte sectors
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Packages Available
8L SON (5 x 6 mm), 32L PLCC
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Fast Erase and Byte-program
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Chip-erase Time: 100 mS (Max.)
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Sector-erase Time: 25 mS (Max.)
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Byte-program Time: 50 碌S (Max.)
-1-
Publication Release Date: February 21, 2002
Revision A1
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