音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

W40S11-23 Datasheet

  • W40S11-23

  • Clock Buffer/Driver

  • 9頁

  • CYPRESS

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

W40S11-23
Clock Buffer/Driver
Features
鈥?Thirteen skew-controlled CMOS clock outputs
(SDRAM0:12)
鈥?Supports three SDRAM DIMMs
鈥?Ideal for high-performance systems designed around
Intel鈥檚 latest chip set
鈥?I
2
C serial configuration interface
鈥?Clock Skew between any two outputs is less than 250 ps
鈥?1- to 5-ns propagation delay
鈥?DC to 133-MHz operation
鈥?Single 3.3V supply voltage
鈥?Low power CMOS design packaged in a 28-pin, 300-mil
SOIC (Small Outline Integrated Circuit)
Key Specifications
Supply Voltages:........................................... V
DD
= 3.3V鹵5%
Operating Temperature:.................................... 0擄C to +70擄C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................V
DD
+ 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns
Output Edge Rate:..............................................
>1.5 V/ns
Output Clock Skew: .................................................. 鹵250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance: ...............................................15鈩?typical
Output Type: ................................................ CMOS rail-to-rail
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output
clock buffer. Output buffer impedance is approximately 15鈩?
which is ideal for driving SDRAM DIMMs.
Block Diagram
Pin Configuration
SDATA
SCLOCK
Serial Port
Device Control
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SOIC
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDATA
[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM7
SDRAM6
GND
GND
[1]
SCLOCK
BUF_IN
SDRAM9
SDRAM10
SDRAM11
SDRAM12
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs
(not CMOS level).
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
September 28, 1999 rev. **

W40S11-23相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！