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W3E16M72S-XBX Datasheet

  • W3E16M72S-XBX

  • DDR SDRAM MCP

  • 16頁(yè)

  • ETC

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W3E16M72S-XBX
16Mx72 DDR SDRAM
FEATURES
!
High Frequency = 200, 250, 266MHz
!
Package:
Preliminary*
BENEFITS
!
40% SPACE SAVINGS
!
Reduced part count
!
Reduced I/O count
鈥?34% I/O Reduction
!
Reduced trace lengths for lower parasitic capacitance
!
Suitable for hi-reliability applications
!
Laminate interposer for optimum TCE match
!
Upgradeable to 32M x 72 density (contact factory for
information)
* This data sheet describes a product that is not fully qualified or characterized
and is subject to change without notice.
鈥?219 Plastic Ball Grid Array (PBGA), 32 x 25mm
!
2.5V 鹵0.2V core power supply
!
2.5V I/O (SSTL_2 compatible)
!
Differential clock inputs (CLK and CLK)
!
Commands entered on each positive CLK edge
!
Internal pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
!
Programmable Burst length: 2,4 or 8
!
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture (one
per byte)
!
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
!
DLL to align DQ and DQS transitions with CLK
!
Four internal banks for concurrent operation
!
Two data mask (DM) pins for masking write data
!
Programmable IOL/IOH option
!
Auto precharge option
!
Auto Refresh and Self Refresh Modes
!
Commercial, Industrial and Military Temperature Ranges
!
Organized as 16M x 72
!
Weight: W3E16M72S-XBX - 2.5 grams typical
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip鈥檚 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the
128MB DDR SDRAM effectively consists of a single 2n-bit
wide, one-clock-cycle data tansfer at the internal DRAM core
and two corresponding
n-bit
wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along
with data, for use in data capture at the receiver. DQS is a
Monolithic Solution
11.9
11.9
11.9
11.9
11.9
Actual Size
W3E16M72S-XBX
22.3
66
TSOP
66
TSOP
66
TSOP
66
TSOP
66
TSOP
White Electronic Designs
W3E16M72S-XBX
25
S
A
V
I
N
G
S
40%
34%
32
Area
I/O
Count
November 2003 Rev. 4
5 x 265mm2 = 1328mm2
5 x 66 pins = 330 pins
1
800mm2
219 Balls
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com

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