White Electronic Designs
W3DG7232V-D2
PRELIMINARY*
256MB 鈥?32Mx72 SDRAM, REGISTER and SPD, w/PLL
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V
鹵
0.3V Power Supply
168 Pin DIMM JEDEC
NOTE: Consult factory for availability of:
鈥?Lead-Free Products
鈥?Vendor source control options
鈥?Industrial temperature options
* This product is under development, is not quali鏗乪d or characterized and is subject to
change without notice.
DESCRIPTION
The W3DG7232V is a 32Mx72 synchronous DRAM module
which consists of nine 32Meg x 8 SDRAM components
in TSOP II package, two 18 bit Drive ICs for input control
signal and one 2Kb EEPROM in an 8 pin TSSOP package
for Serial Presence Detect which are mounted on a 168
pin DIMM multilayer FR4 Substrate.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FRONT
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
CC
WE#
DQMB0
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
BACK
DQMB1
CS0#
DNU
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
CC
V
CC
CK0
V
SS
DNU
CS2#
DQMB2
DQMB3
DNU
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
PIN
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
FRONT
DQ18
DQ19
V
CC
DQ20
NC
*VREF
*CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
*CK2
NC
NC
**SDA
**SCL
V
CC
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
BACK
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
CC
CAS#
DQMB4
PIN
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
BACK
DQMB5
*CS1#
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
CC
*CK1
A12
V
SS
CKE0
*CS3#
DQMB6
DQMB7
*A13
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
1
PIN NAMES
BACK
DQ50
DQ51
V
CC
DQ52
NC
*V
REF
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
*CK3
NC
**SA0
**SA1
**SA2
V
CC
PIN
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
A0 鈥?A12
BA0-1
DQ0-63
CB0-7
CK0
CKE0
CS0#, CS2#
RAS#
CAS#
WE#
DQMB0-7
V
CC
V
SS
*V
REF
REGE
SDA
SCL
SA0-2
DNU
NC
Address Input (Multiplexed)
Select Bank
Data Input/Output
Check Bit (Data-In/Data-Out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQMB
Power Supply (3.3V)
Ground
Power Supply for Reference
Register Enable
Serial Data I/O
Serial Clock
Address in EEPROM
Do Not Use
No Connect
* These pins are not used in this module.
** These pins should be NC in the system which does
not support SPD.
February 2005
Rev. 1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.wedc.com
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