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W39L512-90 Datasheet

  • W39L512-90

  • 64K 8 COMS FLASH MEMORY

  • 300.11KB

  • 25頁

  • WINBOND

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W39L512
64K
脳
8 CMOS FLASH MEMORY
1. GENERAL DESCRIPTION
The W39L512 is a 512Kbit, 3.3-volt only CMOS flash memory organized as 64K
脳
8 bits. For flexible
erase capability, the 512Kbits of data are divided into 16 small even pages with 4 Kbytes. The byte-
wide (脳 8) data appears on DQ7
鈭?/div>
DQ0. The device can be programmed and erased in-system with a
standard 3.3V power supply. A 12-volt V
PP
is not required. The unique cell architecture of the
W39L512 results in fast program/erase operations with extremely low current consumption (compared
to other comparable 3.3-volt flash memory products). The device can also be programmed and erased
by using standard EPROM programmers.
2. FEATURES
鈥?/div>
Single 3.3-volt operations
鈭?/div>
3.3-volt Read
鈭?/div>
3.3-volt Erase
鈭?/div>
3.3-volt Program
鈥?/div>
Flexible 4K-page size can be used as
Parameter Blocks
鈭?/div>
1K/10K
鈥?/div>
Typical program/erase cycles:
鈥?/div>
Twenty-year data retention
鈥?/div>
Low power consumption
鈥?/div>
Fast Program operation:
鈭?/div>
Byte-by-Byte programming: 50
碌S
(max.)
Fast Erase operation: 100 mS (max.)
16 even pages with 4K bytes
Any individual page can be erased
鈭?/div>
Optional 8K byte Top/Bottom Boot Block with
lockout protection
鈥?/div>
鈭?/div>
Active current: 10 mA (typ.)
鈭?/div>
Standby current: 15
碌A
(typ.)
鈥?/div>
End of program detection
鈥?/div>
Read access time: 70/90 nS
鈥?/div>
鈥?/div>
鈭?/div>
Software method: Toggle bit/Data polling
鈥?/div>
TTL compatible I/O
鈥?/div>
JEDEC standard byte-wide pinouts
鈥?/div>
Available packages: 32-pin PLCC and
鈥?/div>
Hardware protection:
32-pin STSOP (8 x 14 mm)
-1-
Publication Release Date: July 9, 2002
Revision A2

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