W39L020
256K
脳
8 CMOS FLASH MEMORY
1. GENERAL DESCRIPTION
The W39L020 is a 2Mbit, 3.3-volt only CMOS flash memory organized as 256K
脳
8 bits. For flexible
erase capability, the 2Mbits of data are divided into 4 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The byte-wide (脳 8) data appears on DQ7
鈭?/div>
DQ0.
The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt
V
PP
is not required. The unique cell architecture of the W39L020 results in fast program/erase
operations with extremely low current consumption (compared to other comparable 3.3-volt flash
memory products). The device can also be programmed and erased by using standard EPROM
programmers.
2. FEATURES
鈥?/div>
Single 3.3-volt operations
鈭?/div>
3.3-volt Read
鈭?/div>
3.3-volt Erase
鈭?/div>
3.3-volt Program
鈥?/div>
Hardware protection:
鈭?/div>
Optional 16K byte or 64K byte Top/Bottom
Boot Block with lockout protection
鈥?/div>
鈥?/div>
Fast Program operation:
鈭?/div>
Byte-by-Byte programming: 50
碌S
(max.)
Fast Erase operation:
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Chip Erase cycle time: 100 mS (max.)
鈭?/div>
Sector Erase cycle time: 25mS (max.)
鈭?/div>
Page Erase cycle time: 25mS (max.)
Flexible 4K-page size can be used as
Parameter Blocks
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Typical program/erase cycles: 1K/10K
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Twenty-year data retention
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Low power consumption
鈥?/div>
鈭?/div>
Active current: 10 mA (typ.)
鈭?/div>
Standby current: 5
碌A(chǔ)
(typ.)
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End of program detection
鈥?/div>
Read access time: 70/90 nS
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4 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
Any individual sector or page can be erased
鈭?/div>
Software method: Toggle bit/Data polling
鈥?/div>
TTL compatible I/O
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JEDEC standard byte-wide pinouts
鈥?/div>
Available packages: 32L PLCC, 32L TSOP (8 x
20 mm) and 32L STSOP (8 x 14 mm)
-1-
Publication Release Date: November 11, 2002
Revision A4
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