W311
FTG for VIA鈩?Pro-266 DDR Chipset
Features
鈥?Maximized EMI Suppression using Cypress鈥檚 Spread
Spectrum Technology
鈥?System frequency synthesizer for VIA Pro-2000
鈥?Programmable clock output frequency with less than 1
MHz increment
鈥?Integrated fail-safe Watchdog Timer for system
recovery
鈥?Automatically switch to HW selected or SW
programmed clock frequency when Watchdog Timer
time-out
鈥?Capable of generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
鈥?Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
鈥?Vendor ID and Revision ID support
鈥?Programmable drive strength for CPU and PCI output
clocks
鈥?Programmable output skew between CPU, AGP and PCI
鈥?Supports Intel
廬
Celeron
廬
and Pentium
廬
III class
processor
鈥?Three copies of CPU output
鈥?Nine copies of PCI output
鈥?One 48-MHz output for USB
鈥?One 24-MHz or 48-MHz output for SIO
鈥?Two buffered reference outputs
鈥?Three copies of APIC output
鈥?Supports frequencies up to 200MHz
鈥?SMBus Interface for programming
鈥?Power management control inputs
鈥?Available in 48-pin SSOP
Key Specifications
CPU Cycle-to-cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew........................................... 175 ps
PCI Cycle-to-cycle Jitter: ............................................. 500 ps
PCI to PCI Output Skew:............................................. 500 ps
Block Diagram
Pin Configuration
[1]
Note:
1. Signals marked with * have internal pull-up resistors
Cypress Semiconductor Corporation
Document #: 38-07703 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised March 14, 2005
next