鈥?/div>
+14V erase/+12V programming voltage
Fully static operation
Output level : 3.3V compatible output
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 32-pin 600 mil DIP and
PLCC
PIN CONFIGURATIONS
Vpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
25
24
23
22
21
20
19
18
17
Vcc
PGM
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
BLOCK DIAGRAM
PGM
CE
OE
CONTROL
OUTPUT
BUFFER
Q0
.
Q7
7 32-pin DIP 26
A0
.
A17
V
CC
GND
V
PP
CORE
DECODER
ARRAY
/
A A A V V P A
1 1 1 p c G 1
2 5 6 p c M 7
3 2 1 3 3 3
2 1 0
29
28
27
26
32-pin PLCC
25
24
23
1 1 1 1 1 2 22
5 6 7 8 9 0 21
PIN DESCRIPTION
SYMBOL
A0鈭扐17
Q0鈭扱7
CE
OE
PGM
V
PP
V
CC
GND
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
A7
A6
A5
A4
A3
A2
A1
A0
Q0
4
5
6
7
8
9
10
11
12 1
13 4
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q Q G Q Q Q Q
1 2 N 3 4 5 6
D
-1-
Publication Release Date: March 1999
Revision A1