Preliminary W26B02
128K
脳
16 CMOS STATIC RAM
GENERAL DESCRIPTION
The W26B02 is a normal-speed, very low-power CMOS static RAM organized as 131072
脳
16 bits that
operates on a wide voltage range from 2.7V to 3.6V power supply. The W26B02, W26B02-LE and
W26B02-LI, can meet the requirement of various operating temperature. This device is manufactured
using Winbond鈥?high performance CMOS technology.
s
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low power consumption
Access time: 70 nS
2.7V to 3.6V supply voltage
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
鈥?/div>
Battery back-up operation capability
鈥?/div>
Data retention voltage: 1.5V (min.)
鈥?/div>
Data byte control
鈭?/div>
#LB (I/O1
鈭?/div>
I/O8), #UB (I/O9
鈭?/div>
I/O16)
鈥?/div>
Available packages: 44-pin type two TSOP,
and TFBGA
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN.
A4
A3
A15
A14
R
O
W
D
E
C
O
D
E
R
PRECHARGE CKT.
CORE CELL ARRAY
1024 ROWS
128 X 16 COLUMNS
A4
A3
A2
A1
A0
#CS
I/O1
I/O2
I/O3
I/O4
V
DD
V
SS
I/O5
I/O6
I/O7
I/O8
#WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-pin
TSOP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
#OE
#UB
#LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
DD
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
A16
A1
A2
A0
A13
I/O1
:
I/O16
DATA
CNTRL.
CLK
GEN.
I/O CKT.
COLUMN DECODER
A7 A6
A5 A8 A9 A10 A11 A12
#WE
#CS
#UB
#LB
#OE
PIN DESCRIPTION
SYMBOL
A0
鈭?/div>
A16
I/O1
鈭?/div>
I/O16
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select
Write Enable Input
Lower byte select
Upper byte select
Output Enable Input
Power Supply
Ground
Internet Connection
No Connection
48-pin TFBGA TOP VIEW
1
#LB
I/O9
I/O10
V
SS
V
DD
I/O15
I/O16
NC
A
B
C
D
E
F
G
H
2
#OE
#UB
I/O11
I/O12
I/O13
I/O14
NC
A8
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
#CS
I/O2
I/O4
I/O5
I/O6
#WE
A11
6
NC
I/O1
I/O3
V
DD
V
SS
I/O7
I/O8
NC
#CS
#WE
#LB
#UB
#OE
V
DD
V
SS
IC
NC
-1-
Publication Release Date: February 6, 2002
Revision A1
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