0
W245-30
Frequency Multiplying, Peak Reducing EMI Solution
Features
鈥?Cypress PREMIS鈩?family offering
鈥?Generates an EMI optimized clocking signal at the out-
put
鈥?Selectable output frequency range
鈥?Single 1.25%, 2.5%, 5% or 10% down or center spread
output
鈥?Integrated loop filter components
鈥?Operates with a 3.3 or 5V supply
鈥?Low power CMOS design
鈥?Available in 20-pin SSOP (Small Shrunk Outline Pack-
age)
Key Specifications
Supply Voltages:......................................... V
DD
= 3.3V鹵0.3V
or V
DD
= 5V鹵10%
Frequency range: ........................... 13 MHz < F
in
< 120 MHz
Cycle to Cycle Jitter: .........................................250 ps (max)
Output duty cycle: .................................40/60% (worst case)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
[1, 2]
SSOP
X1
XTAL
Input
X2
W245-30
SDATA
SCLK
IIC Interface
Spread Spectrum
Output
(EMI suppressed)
X1
X2
AVDD
MW0^
SDATA
OR1^
SCLK
GND
OR2*
SSON#^
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
REFOUT
VDD
GND
IR1*
IR2*
SSOUT
MW1*
GND
VDD
MW2^
W245-30
3.3V or 5.0V
Oscillator or
Reference Input
X1
W245-30
SDATA
IIC Interface
SCLK
Spread Spectrum
Output
(EMI suppressed)
Notes:
1. Pins marked with ^ are internal pull-down resistors with
weak 250 k鈩?
2. Pins marked with * are internal pull-up resistors with weak
80 k鈩?
Cypress Semiconductor Corporation
Document #: 38-07229 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 13, 2002
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