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W233 Datasheet

  • W233

  • Clocks and Buffers

  • 180.27KB

  • 16頁

  • ETC

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PRELIMINARY
W233
Spread Spectrum FTG for VIA Mobile K7 Chipset
Features
鈥?Maximized EMI Suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?Single-chip system frequency synthesizer for VIA Mo-
bile K7 chipset
鈥?Two copies of CPU output
鈥?Seven copies of PCI output
鈥?One 48-MHz output for USB
鈥?One 24-MHz or 48-MHz output for SIO
鈥?Three buffered reference outputs
鈥?Six SDRAM outputs provide support for three SODIMMs
鈥?Supports frequencies up to 166 MHz
鈥?SMBus interface for programming
鈥?Power management control inputs
鈥?Available in 48-pin SSOP
Table 1. Pin Selectable Frequency
Input Address
FS3
FS2
FS1
FS0
CPU
(MHz)
PCI
(MHz)
Spread
Spectrum
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133.3
100.0
133.3
100.0
133.3
100.0
133.3
100.0
95.0
102.0
104.0
106.0
108.0
110.0
111.0
112.0
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
31.7
34.0
34.6
35.3
36.0
36.6
37.0
37.3
OFF
OFF
鹵0.5%
鹵0.5%
鈥?.5%
鈥?.5%
鹵0.25%
鹵0.25%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DD
: .........................................................................3.3V鹵5%
SDRAMIN to SDRAM0:5 Delay: ............................2.0 ns typ.
Block Diagram
VDD_REF
Stop
Clock
Control
REF0_2X
REF1
REF2/FS3*
I/O Pin
Control
Pin Configuration
[1]
VDD_REF
X1
X2
*FS2/PCI_F
*FS1/PCI0
VDD_PCI
GND_PCI
PCI1
PCI2
PCI3
PCI4
PCI5
GND_PCI
VDD_PCI
PCI6
*SDRAM_STOP#
*PCI_STOP#
SDRAMIN
VDD_CORE
GND_CORE
GND_48MHz
*FS0/48MHz
*SEL24_48#/24_48MHz
VDD_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0_2X
REF1
REF2/FS3*
GND_REF
GND_CPU
VDD_CPU
CPU_CS
CPUT0_F
CPUC0_F
CPU_STOP#*
STOP_CLK#*
SDRAM0
SDRAM1
VDD_SDRAM
GND_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
VDD_SDRAM
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
X1
X2
XTAL
OSC
CPU_STOP#
VDD_CPU
CLK_STOP#
Stop
Clock
Control
PLL 1
梅2,3,4
CPU_CS
CPUT0_F
CPUC0_F
VDD_PCI
PCI_F/FS2
PCI0/FS1
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
VDD_48MHz
48MHz/FS0
W233
Stop
Clock
Control
PCI_STOP#
SDATA
SCLK
SMBus
Logic
PLL2
梅2
SDRAM_STOP#
SDRAMIN
*SEL24_48#/24_48MHz
Stop
Clock
Control
VDD_SDRAM
SDRAM0:5
SDRAM_F
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.
7
Cypress Semiconductor Corporation
Document #: 38-07250 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 21, 2002

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