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W228BH Datasheet

  • W228BH

  • CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC

  • 174.43KB

  • 16頁

  • ETC

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W228B
FTG for Integrated Core Logic with 133-MHz FSB
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?Two copies of CPU clock at 66/100/133 MHz
鈥?Thirteen copies of 100-MHz SDRAM clocks
鈥?Two copies of PCI clock
鈥?One copy of APIC clock at 33 MHz, synchronous to CPU
clock
鈥?Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
鈥?Three copies of 3V 66-MHz fixed clock
鈥?One copy of 14.31818-MHz reference clock
鈥?Power down control
鈥?SMBus interface for turning off unused clocks
CPU, 3V66 Output Skew:............................................175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................鹵0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................鹵0.5 ns
Table 1. Pin Selectable Functions
Tristate#
0
0
1
1
1
1
FSEL0
0
1
0
1
0
1
FSEL1
x
x
0
0
1
1
CPU
Three-state
Test
66 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Three-state
Test
100 MHz
100 MHz
133 MHz
100 MHz
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, SDRAM Output Skew: ...................................... 250 ps
Block Diagram
VDDQ3
Pin Configuration
[1]
APIC
VDDQ2
GND
REF0/FSEL1*
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
3V66_AGP
GND
VDDQ3
PCI0_ICH
PCI1
GND
FSEL0
GNDA
VDDA
PWRDWN#
SCLK
SDATA
GND
VDDQ3
USB
DOT
Tristate#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
GND
CPU0
CPU1
GND
SDRAM0
SDRAM1
VDDQ3
GND
SDRAM2
SDRAM3
SDRAM4
VDDQ3
GND
SDRAM5
SDRAM6
VDDQ3
GND
SDRAM7
SDRAM8
SDRAM9
VDDQ3
GND
SDRAM10
SDRAM11
VDDQ3
GND
SDRAM12
X1
X2
XTAL
OSC
PLL REF FREQ
REF0/FSEL1
VDDQ2
SDATA
SCLK
SMBus
Logic
Divider,
Delay,
and
Phase
Control
Logic
2
CPU0:1
W228B
APIC
VDDQ3
FSEL1:0
VDDA
PLL 1
2
3V66_0:1
3V66_AGP
PCI0_ICH
Tristate#
PCI1
SDRAM0:12
13
PWRDWN#
VDDQ3
USB
DOT
VDDA
PLL2
Note:
1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07180 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 4. 2001

W228BH相關(guān)型號PDF文件下載

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    下載
  • 英文版
    FTG for Integrated Core Logic with 133-MHz FSB
    Cypress
  • 英文版
    CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC
    ETC

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