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W216 Datasheet

  • W216

  • Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

  • 14頁(yè)

  • CYPRESS

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PRELIMINARY
W216
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
鈥?Maximized EMI Suppression using Cypress鈥檚 Spread
Spectrum Technology
鈥?Single chip system FTG for Intel
廬
440BX AGPset and
VIA Apollo Pro-133
鈥?Three copies of CPU output
鈥?Seven copies of PCI output
鈥?One 48-MHz output for USB / One 24-MHz for SIO
鈥?Two buffered reference outputs
鈥?Two IOAPIC outputs
鈥?Seventeen SDRAM outputs provide support for 4
DIMMs
鈥?Supports frequencies up to 150 MHz
鈥?I
2
C鈩?interface for programming
鈥?Power management control inputs
Table 1. Mode Input Table
Mode
0
1
Pin 3
PCI_STOP#
REF0
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ.
V
DDQ3
: .................................................................... 3.3V鹵5%
V
DDQ2
: .................................................................... 2.5V鹵5%
SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 2. Pin Selectable Frequency
Input Address
CPU_F, 1:2
PCI_F, 0:5
FS3 FS2 FS1 FS0
(MHz)
(MHz)
1
1
1
1
133.3
33.3 (CPU/4)
1
1
1
0
124
31 (CPU/4)
1
1
0
1
150
37.5 (CPU/4)
1
1
0
0
140
35 (CPU/4)
1
0
1
1
105
35 (CPU/3)
1
0
1
0
110
36.7 (CPU/3)
1
0
0
1
115
38.3 (CPU/3)
1
0
0
0
120
40 (CPU/3)
0
1
1
1
100
33.3 (CPU/3)
0
1
1
0
Reserved
0
1
0
1
112
37.3 (CPU/3)
0
1
0
0
103
34.3 (CPU/3)
0
0
1
1
66.8
33.4 (CPU/2)
0
0
1
0
83.3
41.7 (CPU/2)
0
0
0
1
75
37.5 (CPU/2)
0
0
0
0
Reserved
Block Diagram
VDDQ3
REF0/(PCI_STOP#)
X1
X2
XTAL
OSC
REF1/FS2
PLL Ref Freq
Stop
Clock
Control
Pin Configuration
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
[1]
I/O Pin
Control
CLK_STOP#
VDDQ2
IOAPIC_F
IOAPIC0
VDDQ2
CPU_F
PLL 1
梅2,3,4
Stop
Clock
Control
CPU1
CPU2
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
PCI2
PCI3
Stop
Clock
Control
SDATA
SCLK
I
2
C
Logic
PCI4
PCI5
VDDQ3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ2
CPU2
GND
CLK_STOP#
SDRAM_F
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
PLL2
Stop
Clock
Control
48MHz/FS1
24MHz/FS0
VDDQ3
SDRAM0:15
16 SDRAM_F
SDRAMIN
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
W216
Intel is a registered trademark of Intel Corporation. I
2
C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
October 27, 1999, rev. **

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  • 英文版
    Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
    CYPRESS
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    CYPRESS [C...

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