PRELIMINARY
W215B
Notebook PC System Frequency Generator for K6 Processors
Features
鈥?Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, USB plus 14.318 MHz (REF0:1)
鈥?MODE input pin selects optional power management
input control pins (reconfigures pins 26 and 27)
鈥?Two fixed outputs separately selectable as 24-MHz or
48-MHz (default = 48-MHz)
鈥?V
DDQ3
= 3.3V鹵5%, V
DDQ2
= 3.3V鹵5%
鈥?Uses external 14.318-MHz crystal
鈥?Available in 48-pin TSSOP (6.1-mm)
鈥?/div>
10鈩?CPU output impedance
Table 1. Pin Selectable Frequency
95/100_SEL
0
1
CPU, SDRAM
Clocks (MHz)
95.0
100.0
PCI Clocks
CPU/3
CPU/3
Block Diagram
VDDQ3
REF0
X1
X2
XTAL
OSC
PLL Ref Freq
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU_2.5#
www.DataSheet4U.com
Pin Configuration
REF1
REF0
GND
X1
X2
MODE
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
GND
95/100_SEL
Reserved
Reserved
VDDQ3
48/24MHZ
48/24MHZ
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
CPU_2.5#
VDDQ2
IOAPIC
PWR_DWN#
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
VDDQ3
REF1
W215B
CPU1
Stop
Output
Control
CPU2
CPU3
VDDQ3
SDRAM0
SDRAM1
SDRAM2
MODE
I/O
Control
95/100_SEL
PLL 1
SDRAM3
SDRAM4
SDRAM5
SDRAM6/CPUSTOP#
SDRAM7/PCISTOP#
PCI_F
Stop
Output
Control
PCI0
PCI1
PCI2
PWR_DWN#
Power
Down
Control
PCI3
PCI4
PCI5
PLL2
48/24MHZ
48/24MHZ
Cypress Semiconductor Corporation
Document #: 38-07222 Rev. *A*
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 15, 2002
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