音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

W208D Datasheet

  • W208D

  • Clocks and Buffers

  • 172.22KB

  • 14頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

PRELIMINARY
W208D
FTG for Integrated Core Logic with 133-MHz FSB
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?Low jitter and tightly controlled clock skew
鈥?Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
鈥?Three copies of CPU clock at 66/100 MHz
鈥?Nine copies of 100-MHz SDRAM clocks
鈥?Eight copies of PCI clock
鈥?Two copies of synchronous APIC clock
鈥?Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
鈥?Two copies of 66-MHz fixed clock
鈥?One copy of 14.31818-MHz reference clock
鈥?Power down control
鈥?I
2
C鈩?interface for turning off unused clocks
APIC, 48-MHz, SDRAM Output Skew: ........................250 ps
CPU, 3V66 Output Skew:............................................175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................鹵0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................鹵0.5 ns
Table 1. Pin Selectable Functions
SEL133
X
X
0
0
1
1
SEL1
0
0
1
1
1
1
SEL0
0
1
0
1
0
1
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Reserved
133-MHz CPU
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
Block Diagram
VDDQ3
Pin Configuration
[1]
REF/SEL133*
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDDQ3
GND
GND
USB
DOT
VDDQ3
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
PWRDWN#
SCLK
SDATA
SEL1
X1
X2
XTAL
OSC
PLL REF FREQ
REF/SEL133
VDDQ2
SDATA
SCLK
I
2
C
Logic
Divider,
Delay,
and
Phase
Control
Logic
2
CPU0:1
CPU2_ITP
APIC0:1
VDDQ3
W208D
2
SEL0:1
PLL 1
2
3V66_0:1
PCI0_ICH
PCI1:7
7
DCLK
PWRDWN#
8
SDRAM0:7
PLL2
VDDQ3
USB
DOT
Note:
1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
I
2
C is a trademark of Phillips Corporation. Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07228 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 21, 2002

W208D相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    FTG for Integrated Core Logic with 133-MHz FSB
    Cypress

您可能感興趣的PDF文件資料

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！