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W207B-H Datasheet

  • W207B-H

  • CPU System Clock Generator

  • 153.67KB

  • 16頁

  • ETC

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W207B
Spread Spectrum FTG for SiS540 and 630 Chipsets
Features
鈥?Maximized EMI Suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?Single-chip system frequency synthesizer for SiS540
and SiS630 core logic chip sets
鈥?Three copies of CPU output
鈥?Seven copies of PCI output
鈥?One 48-MHz output for USB
鈥?One 24-/48-MHz selectable output for SIO
鈥?Two buffered reference outputs
鈥?14 SDRAM outputs provide support for 3 DIMMs SMBus
interface for programming
Table 1. Pin Selectable Frequency
CPU SDRAM
PC
FS3 FS2 FS1 FS0 (MHz) (MHz) (MHz)
0
0
0
0
66.6
100.0
33.3
0
0
0
1
100.2
100.2
33.4
0
0
1
0
150.3
100.2
37.6
0
0
1
1
133.6
100.2
33.4
0
1
0
0
66.8
111.3
33.4
0
1
0
1
100.2
133.6
33.4
0
1
1
0
100.2
150.3
33.4
0
1
1
1
133.3
133.3
33.3
1
0
0
0
66.6
66.6
33.3
1
0
0
1
83.3
83.3
31.2
1
0
1
0
97.0
97.0
32.3
1
0
1
1
95.0
95.0
31.7
1
1
0
0
95.0
126.7
31.7
1
1
0
1
112.0
112.0
37.3
1
1
1
0
122.0
91.5
30.5
1
1
1
1
122.0
122.0
30.5
SS
鈥?.6%
鹵0.45%
OFF
鹵0.45%
OFF
鹵0.45%
OFF
鈥?.6%
鈥?.6%
OFF
鈥?.6%
鹵0.45%
OFF
OFF
鈥?.6%
鈥?.6%
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
CPU to PCI Output Skew (CPU leads): ................... 1 to 4 ns
CPU to SDRAM Output Skew: .................................... 500 ps
V
DDQ3
: .................................................................... 3.3V鹵5%
V
DDQ2
: .................................................3.3V鹵5% or 2.5V鹵5%
Block Diagram
VDDQ3
REF1
X1
X2
XTAL
OSC
PLL Ref Freq
Pin Configuration
[1]
REF0_2X/FS3
梅
13
SDRAM0:13
VDDQ2
PLL 1
梅
3
CPU0:2
VDDQ3
PCI0/FS1
PCI1/FS2
PCI2
PCI3
PCI4
SDATA
SCLK
VDDQ3
REF0_2X/FS3*
GND
X1
X2
VDDQ3
PCI0/FS1*
PCI1/FS2*
PCI2
GND
PCI3
PCI4
PCI5
PCI6
VDDQ3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SMBus
SDATA
SCLK
{
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1
VDDQ2
CPU0
CPU1
GND
CPU2
VDDQ3
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM7
SDRAM6
VDDQ3
SDRAM5
SDRAM4
VDDQ3
48MHz_2X/FS0*
SIO/CPU3.3#_2.5*
W207B
I C
Logic
2
PCI5
PCI6
Note:
1. Internal 100-k鈩?pull-down resistors present on inputs marked with *.
Design should not rely solely on internal pull-down resistors to set
I/O pins LOW.
PLL2
x1/梅2
VDDQ3
48MHz_2X/FS0
SIO/CPU3.3#_2.5
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
November 16, 2000, rev. *B

W207B-H相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Spread Spectrum FTG for SiS540 and 630 Chipsets
    Cypress
  • 英文版
    CPU System Clock Generator
    ETC

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