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W204 Datasheet

  • W204

  • Clocks and Buffers

  • 16頁

  • ETC

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PRELIMINARY
W204
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
鈥?Maximized EMI suppression using Cypress鈥檚 spread
spectrum technology
鈥?Optimized system frequency synthesizer for 440BX and
VIA Apollo Pro-133
鈥?Four copies of CPU output
鈥?Eight copies of PCI clock (synchronous w/CPU output)
鈥?Two copies of 14.318-MHz IOAPIC output and three
buffered copies of 14.318-MHz reference input
鈥?One copy of 48-MHz USB output
鈥?Selectable 24-/48-MHz clock-through-resistor
strapping
鈥?Power management control input pins
鈥?Programmable clock outputs up to 155 MHz via SMBus
interface (32 selectable frequencies)
CPU Cycle to Cycle Jitter: ..........................................250 ps
CPU0:3 Output Skew: ................................................175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
CPU to PCI Output Skew: ............... 1.0鈥?.0 ns (CPU Leads)
REF0/SEL48#, SCLK,SDATA:........................... 250K pull-up
FS1:...............................................................250K pull-down
FS0:...................................................No pull-up or pull-down
Test mode and output three-state through SMBus interface
Table 1. Pin Selectable Frequency
FS1
1
1
0
0
Supply Voltages: ..................................... VDDQ3 = 3.3V鹵5%
VDDQ2 = 2.5V鹵5%
FS0
1
0
1
0
CPU(0:3)
133.3 MHz
105 MHz
100 MHz
66.8 MHz
PCI
33.3 MHz
35 MHz
33.3 MHz
33.3 MHz
Key Specifications
Block Diagram
VDDQ3
REF0/SEL48#
X1
X2
XTAL
OSC
PLL Ref Freq
VDDCORE0/1
GNDCORE0/1
REF1
REF2
GND
VDDQ2
APIC0
APIC1
GND
VDDQ2
CPU0
Stop
Clock
Control
FS0:1
PLL 1
梅2/梅3
SPREAD#
CPU1
GND
VDDQ2
CPU2
CPU3
GND
VDDQ3
PCI_F
Stop
Clock
Control
PCI_STOP#
PCI1
PCI2
PCI3
GND
VDDQ3
PCI4
I
2
C
Logic
Power
Down
Control
PLL2
PCI5
PCI6
PCI7
GND
VDDQ3
48MHz
24_48MHz/FS1
GND
Pin Configuration
REF0/SEL48#
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
24_48MHz/FS1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
[1]
CPU_STOP#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
REF2
VDDQ2
APIC0
APIC1
GND
NC
VDDQ2
CPU0
CPU1
GND
VDDQ2
CPU2
CPU3
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SDATA
SCLK
FS0
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.
SDATA
SCLK
PWR_DWN#
Cypress Semiconductor Corporation
Document #: 38-07264 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 22, 2002

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