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W199 Datasheet

  • W199

  • Spread Spectrum FTG for VIA Apollo Pro-133

  • 156.82KB

  • 14頁

  • CYPRESS

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PRELIMINARY
W199
Spread Spectrum FTG for VIA Apollo Pro-133
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum Technology
鈥?Single-chip system frequency synthesizer for VIA
Apollo Pro-133
鈥?Two copies of CPU output
鈥?Six copies of PCI output
鈥?One 48-MHz output for USB
鈥?One 24-MHz output for SIO
鈥?Two buffered reference outputs
鈥?One IOAPIC output
鈥?13 SDRAM outputs provide support for 3 DIMMs
鈥?Supports frequencies up to 150 MHz
鈥?I
2
C鈩?interface for programming
鈥?Power management control inputs
鈥?Available in 48-pin SSOP
Table 1. Mode Input Table
Mode
0
1
Table 2. Pin Selectable Frequency
Input Address
FS3
1
1
1
1
1
1
1
1
0
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
: .................................................................... 3.3V鹵5%
V
DDQ2
: .................................................................... 2.5V鹵5%
SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
0
0
0
0
0
0
0
FS2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
[1]
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU_F
CPU1
VDDQ2
CLK_STOP#
SDRAM_F
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
Pin 2
PCI_STOP#
REF0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU_F,
CPU1 (MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
124
PCI_F, 1:5
(MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Key Specifications
Logic Block Diagram
VDDQ3
REF0/(PCI_STOP#)
X1
X2
XTAL
OSC
PLL Ref Freq
Pin Configuration
REF1/FS2
VDDQ2
IOAPIC
I/O Pin
Control
Stop
Clock
Control
CLK_STOP#
VDDQ2
Stop
Clock
Control
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
梅2
PLL 1
梅2,3,4
Stop
Clock
Control
SDATA
SCLK
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDATA
I
2
C
SCLK
{
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W199
I C
Logic
PLL2
2
SDRAMIN
Stop
Clock
Control
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
I
2
C is a trademark of Philips Corporation.
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
October 19, 1999, rev. **

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