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W194 Datasheet

  • W194

  • Frequency Multiplier and Zero Delay Buffer

  • 6頁

  • CYPRESS

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W194
Frequency Multiplier and Zero Delay Buffer
Features
鈥?Two outputs
鈥?Configuration options allow various multiplications of
the reference frequency鈥攔efer to
Table 1
to determine
the specific option which meets your multiplication
needs
鈥?Available in 8-pin SOIC package
Table 1. Configuration Options
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
Operating Voltage: .............................. 3.3V鹵5% or 5.0鹵10%
Operating Range: .......................10 MHz < f
OUT1
< 133 MHz
Absolute Jitter: ......................................................... 鹵500 ps
Output to Output Skew: .............................................. 250 ps
Propagation Delay: ................................................... 鹵350 ps
Propagation delay is affected by input rise time.
OUT2
OUT2
OUT2
FS0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
OUT1
2 X REF
4 X REF
REF
8 X REF
4 X REF
8 X REF
2 X REF
16 X REF
OUT2
REF
2 X REF
REF/2
4 X REF
2 X REF
4 X REF
REF
8 X REF
Key Specifications
Block Diagram
FBIN
External feedback connection to
OUT1 or OUT2, not both
Pin Configuration
SOIC
FBIN
IN
GND
1
2
3
4
8
7
6
5
OUT2
VDD
OUT1
FS1
FS0
FS1
梅Q
FS0
IN
Reference
Input
Phase
Detector
Charge
Pump
Loop
Filter
Output
Buffer
VCO
梅2
Output
Buffer
OUT1
OUT2
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
January 5, 2000, rev. *A

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  • 英文版
    Frequency Multiplier and Zero Delay Buffer
    CYPRESS
  • 英文版
    Frequency Multiplier and Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Miscellaneous Clock Generator
    ETC

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