鈥?/div>
Cypress PREMIS鈩?family offering
鈥?Generates an EMI optimized clocking signal at the
output
鈥?Selectable output frequency range
鈥?Single 1.25% or 3.75% down or center spread output
鈥?Integrated loop filter components
鈥?Operates with a 3.3 or 5V supply
鈥?Low power CMOS design
鈥?Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Table 1. Modulation Width Selection
SS%
0
1
W182
Output
F
in
鈮?/div>
F
out
鈮?/div>
F
in
鈥?1.25%
F
in
鈮?/div>
F
out
鈮?/div>
F
in
鈥?3.75%
W182-5
Output
F
in
+ 0.625%
鈮?/div>
F
in
鈮?/div>
鈥?0.625%
F
in
+ 1.875%
鈮?/div>
F
in
鈮?/div>
鈥?.875%
Table 2. Frequency Range Selection
FS2
0
0
1
1
FS1
0
1
0
1
Frequency Range
8 MHz
鈮?/div>
F
IN
鈮?/div>
10 MHz
10 MHz
鈮?/div>
F
IN
鈮?/div>
15 MHz
15 MHz
鈮?/div>
F
IN
鈮?/div>
18 MHz
18 MHz
鈮?/div>
F
IN
鈮?/div>
28 MHz
Key Specifications
Supply Voltages: ........................................... V
DD
= 3.3V鹵5%
or V
DD
= 5V鹵10%
Frequency Range: .............................. 8 MHz
鈮?/div>
F
in
鈮?/div>
28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
1
2
3
4
5
6
14
13
12
11
10
9
8
REFOUT
OE#
SSON#
Reset
VDD
VDD
CLKOUT
W182/W182-5
X1
XTAL
Input
X2
W182
Spread Spectrum
Output
(EMI suppressed)
7
3.3V or 5.0V
Oscillator or
Reference Input
W182
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
June 8, 2000, rev. *A
W182相關(guān)型號PDF文件下載
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