鈮?/div>
40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3 or 5.0V
Pin Configurations
SOIC
W181-01/51
X1
XTAL
Input
CLKIN or X1
NC or X2
GND
SS%
X2
1
2
3
4
8
7
6
5
FS2
FS1
VDD
CLKOUT
40 MHz
Max.
W181
Spread Spectrum
Output
(EMI suppressed)
CLKIN or X1
NC or X2
GND
SS%
1
2
3
4
8
7
6
5
SSON#
FS1
VDD
CLKOUT
W181-02/03
W181-52/53
3.3 or 5.0V
TSSOP
FS2
CLKIN or X1
Oscillator or
Reference Input
NC or X2
GND
NC
SS%
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
NC
FS1
NC
VDD
NC
CLKOUT
W181-01
W181
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-07152 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 25, 2001
next