W155
Spread Spectrum Frequency Timing Generator
Features
鈥?Generates a spread spectrum timing signal (SYSCLK)
and a non-spread signal (USBCLK)
鈥?Requires a 14.318-MHz crystal for operation
鈥?Supports MIPS microprocessor clock frequencies
鈥?Reduces peak EMI by as much as 12 dB
鈥?Integrated loop filter components
鈥?Cycle-to-cycle jitter = 250 ps (max)
鈥?Operates with a 3.3 or 5.0V power supply
鈥?Spread output is selectable from 10 to 133 MHz
鈥?TEST mode supports modulation off (High-Z) and spe-
cial test input reference frequency
鈥?Guaranteed 45/55 duty cycle
鈥?Packaged in a 16-pin, 300-mil-wide SOIC (Small Outline
Integrated Circuit)
Table 1. Frequency Selection (14.318-MHz Reference)
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SYSCLK
(Output Freq.)
133.3 MHz
120 MHz
100 MHz
74.77 MHz
70 MHz
66.6 MHz
60 MHz
50 MHz
40 MHz
33.33 MHz
30 MHz
25 MHz
20 MHz
16.67 MHz
12 MHz
10 MHz
Overview
The W155 incorporates the latest advances in PLL-based
spread spectrum frequency synthesizer technology. By fre-
quency modulating the SYSCLK output with a low-frequency
carrier, peak EMI can be greatly reduced in a system. Use of
this technique allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system that uses the W155, not only is EMI reduced in the
various clock lines, but also in all signals which are synchro-
nized to SYSCLK. Therefore, the benefits of using this tech-
nique increase with the number of address and data lines in
the system.
The W155 is specifically targeted toward MIPS microproces-
sor based systems where EMI is of particular concern. Each
device uses a single 14.318-MHz crystal to generate a select-
able spread spectrum output and an unmodulated 48-MHz
USB Output.
The spreading function can be disabled by taking the SSON#
pin high. Spread percentage can be selected with the SS%
input (see
Table 2
below).
Table 2. Spread Percentage Selection
SS%
0
1
[1]
Spread Percentage
鈥?.25%
鈥?.75%
Pin Configuration
VDD
X1
X2
GND
FS3*
VDD
FS2*
FS1*
1
2
16
15
W155
14
13
12
11
10
9
TEST
VDD
USBCLK/SS%*
GND
SYSCLK
GND
FS0*
SSON#^
3
4
5
6
7
8
Note:
1. Internal pull-up resistor present on inputs marked with 鈥?鈥?and pull-down
resistor present on input marked with 鈥榐鈥?
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
September 29, 1999, rev. **
1
2
3
4
5
6
